Abstract: A test fixture having an adjustable capacitance (10) and a method for testing a semiconductor component using the test fixture (10). The test fixture (10) includes a loadboard (12) having a semiconductor component receiving area (14), and a power supply input terminal (16) capable of receiving an unbuffered constant current bias signal from a power supply (18). A semiconductor component is coupled to the semiconductor component receiving area (14). A switched capacitor network (21) mounted on the test fixture (10) is configured so that a desired load capacitance is coupled to the power supply input terminal (16) when the semiconductor component is initialized. Then the switched capacitor network (21) is configured so that substantially zero capacitance is coupled to the power supply input terminal. Power supply voltage fluctuations are mapped while the semiconductor component is biased with the power supply and receiving a voltage alteration signal from a laser.

Abstract: A method and system for testing programmability of a programmable logic device (PLD) having a programmable AND array. The PLD is bulk programmed and verified. If the bulk programming fails, each row of cells of the AND array is programmed individually and the row-by-row programming of the PLD is verified.

Abstract: A cascode amplifier circuit which generates a fast, stable and accurate bit line voltage is disclosed. According to one exemplary embodiment, the cascode amplifier circuit comprises a transistor having a source connected to a bit line voltage and a drain connected to an output voltage. The cascode amplifier circuit also comprises a differential circuit having an inverting input connected to the bit line voltage, a non-inverting input connected to a reference voltage, and an output connected to a gate of the first transistor. The operation of the transistor and the differential circuit generate a fast, stable the accurate bit line voltage.

Abstract: According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises a tunnel oxide layer, where the tunnel oxide layer is situated on the substrate. The structure further comprises a floating gate situated on the tunnel oxide layer, where the floating gate comprises nitrogen. The floating gate may further comprise polysilicon and may be situated in a floating gate flash memory cell, for example. The nitrogen may suppress oxide growth at first and second end regions of the tunnel oxide layer, for example. The nitrogen may be implanted in the floating gate, for example, at a concentration of between approximately 1013 atoms per cm2 and approximately 1015 atoms per cm2. According to this exemplary embodiment, the structure further comprises an ONO stack situated over the floating gate. The structure may further comprise a control gate situated over the ONO stack.

Abstract: A method for forming a dual inlaid interconnect structure for ICs is disclosed. The method includes forming an etch stop layer, opening a portion of the etch stop layer on an IC die, forming a first dielectric layer, a middle stop layer, a second dielectric layer and a cap layer thereover. The method further comprises patterning the cap, dielectric layers and middle stop layer a via opening down to the etch stop layer that is associated with the opening therein. A trench opening is formed down through the cap and second dielectric layer and stopping on the middle stop layer. The trench/via opening is then filled with a conductive material (e.g., metal). The method may further include forming a barrier layer within the opening of the etch stop layer.

Abstract: A computer chip having on-chip internetworked modules and implementing a network protocol for on-chip and, also preferably, off-chip data transfers. The modules on chip are interconnected through a plurality of on-chip packet-switched local area networks or LANs. The familiar Internet topology may be implemented on-chip with each module being treated as a “host.” A plurality of network interconnect (e.g. routers, gateways, etc.) may also be provided to interconnect the plurality of LANs. The computer chip implements a network protocol for on-chip data transfer. The network protocol may be TCP/IP. In that case, the computer chip itself may be treated as an Internet. This flexible chip architecture in that the computer chip may have modules clustered conveniently according to functionality, and the various modules may interact with one another without overburdening the chip packing density.

Abstract: A memory address generator for a multiport data communication system storing received data packets in a memory having a plurality of storage areas. The data communication system has a plurality of receive ports receiving the data packets and a queue of addresses of a plurality of storage areas in the memory available for storing the received data packets. The address generator generates memory addresses to store the received data packets in the plurality of storage areas of the memory and includes first and second registers. The first register receives an address from the queue of addresses and provides a first part of the memory address, and the second register counts write cycles to the memory and provides the count result as a second part of the memory address.

Abstract: In one illustrative embodiment, the method comprises forming a gate insulation layer above a substrate, forming a layer of polysilicon above the gate insulation layer, implanting a dopant material into the layer of polysilicon, forming an undoped layer of polysilicon above the doped layer of polysilicon and performing an etching process on the undoped layer of polysilicon and the doped layer of polysilicon to define a gate electrode having a width at an upper surface that is greater than a width of the gate electrode at a base of the gate electrode. In further embodiments, the method comprises forming a layer of refractory metal above the gate electrode and performing at least one heating process to form a metal silicide region on the gate electrode structure.

Abstract: A selection circuit for sensing current in a target cell during a memory read operation is disclosed. According to one embodiment, the selection circuit comprises a sensing circuit selector connected to a sensing circuit and a ground selector connected to ground. The ground selector connects a first bit line of the target cell to ground, and the sensing circuit selector connects a second bit line of the target cell to the sensing circuit. The sensing circuit selector also connects a third bit line of a first neighboring cell to the sensing circuit. The first neighboring cell shares the second bit line with the target cell.

Abstract: A method of programming and reading a dual cell memory device. The method includes storing a selected program level in each cell and reading one of the cells to determine a single data value stored by the memory device.

Abstract: A system and method for removing a conductive line from a semiconductor device is disclosed. The conductive line includes a conductive layer and a barrier layer separating the conductive layer from a portion of the semiconductor device. The method and system include exposing a portion of the barrier layer, etching the barrier layer after the barrier layer has been exposed, and lifting off the conductive layer after the barrier layer has been etched.

Abstract: The present invention provides for improved alignment of an opening in a lower dielectric layer with an opening in an upper dielectric layer. This improved alignment is beneficial as it improves the functionality of devices with dual damascene material arrangements, as normal misalignments do not deem the devices inferior or non-functional. Further, the present invention is beneficial as it allows for a designer, such as a microprocessor designer, to depend on more predictable conductive characteristics of contacts between a first conductive region and a second conductive region.

Abstract: Disclosed is a memory storage and retreivel device containing (a) an electrically conductive first electrode; (b) an electrically conductive second electrode; and (c) a layer stack intermediate the first and second electrodes containing (d) at least one active layer containing at least one polymer with variable electrical conductivity; and (e) at least one passive layer containing a material for varying the electrical conductivity of the at least one active layer upon application of an electrical potential difference between the first and second electrodes.

Abstract: A system and method for delaying power to a computer system. The method includes providing a standby signal. The method further includes receiving a power up signal. The method also includes delaying the power up signal. The method further includes passing the power up signal to the computer system after delaying the power up signal. The system includes a detection circuit and a delay circuit. The detection circuit is configured to receive a standby signal from a power supply. The detection circuit is also configured to output a control signal. The delay circuit is coupled to receive the control signal. The delay circuit is configured to output a delayed control signal for the power supply in response to the control signal after a predetermined period of time.

Abstract: A semiconductor device having gate oxide with a first thickness and a second thickness is formed by initially implanting a portion of the gate area of the semiconductor substrate with nitrogen ions and then forming a gate oxide on the gate area. Preferably the gate oxide is grown by exposing the gate area to an environment of oxygen. A nitrogen implant inhibits the rate of SiO2 growth in an oxygen environment. Therefore, the portion of the gate area with implanted nitrogen atoms will grow or form a layer of gate oxide, such as SiO2, which is thinner than the portion of the gate area less heavily implanted or not implanted with nitrogen atoms. The gate oxide layer could be deposited rather than growing the gate oxide layer. After forming the gate oxide layer, polysilicon is deposited onto the gate oxide. The semiconductor substrate can then be implanted to form doped drain and source regions. Spacers can then be placed over the drain and source regions and adjacent the ends of the sidewalls of the gate.

Abstract: An integrated circuit fabrication process including exposing a photoresist layer and providing a hydrophilic layer above the photoresist layer. The photoresist layer is exposed to a pattern of electromagnetic energy. The polymers in the hydrophilic layer can diffuse into the photoresist layer after provision of the hydrophilic layer. The diffusion can lead to plasticization of the photoresist layer polymers in exposed regions relative to unexposed regions. The process can be utilized to form a large variety of integrated circuit structures including via holes, trenches, contact holes and other features with wide process latitude and smooth feature side walls.

Abstract: The present memory includes a plurality of transistors laid out in a number of rows and columns. First and second series-connected transistors are included in a first column, and are connected between first and second bit lines and are respectively associated with first and second word lines. A region between the series-connected first and second transistors is connected to a first bit line. Third and fourth series-connected transistors are included in a second column, and are connected between the second bit line and a third bit line and are respectively associated with third and fourth word lines. A region between the series-connected third and fourth transistors is connected to a second bit line. The first, second, third and fourth transistors are respective parts of first, second, third and fourth rows of transistors.

Abstract: For locating an extrusion from an interconnect, an extrusion monitor structure is formed to surround the interconnect and is separated from the interconnect by a dielectric material. A first via is coupled to the interconnect, and a second via is coupled to the extrusion monitor structure and separated from the first via by a via distance (Lv). The extrusion is located at an extrusion site distance (Lextrusion) from the first via and between the first and second vias to short-circuit the interconnect to the extrusion monitor structure. A resistance (Rtotal) between the first and second vias is measured, and the Lextrusion is determined from a relationship with Rtotal, Lv, and resistivities and dimensions of the interconnect and the extrusion monitor structure.

Abstract: An array of non-volatile memory cells is provided for storing a data pattern and reproducing the data pattern. The array comprises a semiconductor substrate moderately doped with a first type of impurity to enhance conductivity. A plurality of bit lines within the substrate define a plurality of vertical channel regions spaced there between. Each bit line comprises the substrate doped with a second type of impurity to enhance conductivity. Each channel comprises a moderately doped channel region portion adjacent to a first one of the bit lines and a slightly more heavily doped channel region portion adjacent to a second one of the bit lines. A plurality of parallel spaced apart semiconductor word lines are positioned over the substrate and separated from the substrate by an insulator film, a charge storage region, and a second insulator film.

Abstract: A semiconductor structure and a method of determining an overlay error produced during formation of a semiconductor structure is disclosed. The semiconductor structure comprises a first periodic pattern and a second periodic pattern, which overlap with each other, wherein a relative position between the overlapping first and second periodic patterns contains information on the magnitude and the sign of an overlay error in a predefined direction that has been caused during the formation of the first and second periodic patterns. The overlay error is determined by directing a light beam of known optical properties onto the first and second periodic patterns and by analyzing the diffracted beam by comparison with reference data. By providing two differently oriented diffracting areas, each comprising first and second periodic patterns, the overlay error in two dimensions can be determined.