Abstract: A system for regulating nitrided gate oxide layer formation is provided. The system includes one or more light sources, each light source directing light to one or more nitrided gate oxide layers being deposited and/or formed on a wafer. Light reflected from the nitrided gate oxide layers is collected by a measuring system, which processes the collected light. The collected light is indicative of the nitrogen concentration of the respective nitrided gate oxide layers on the wafer. The measuring system provides nitrogen concentration related data to a processor that determines the nitrogen concentration of the respective nitrided gate oxide layers on the wafer. The system also includes one or more nitrided gate oxide layer formers where a nitride gate oxide former corresponds to a respective portion of the wafer and provides for nitrided gate oxide layer formation thereon.

Abstract: A thermal protection circuit for high output power supplies. A power supply circuit includes a switching control circuit coupled to a switching regulator circuit. The switching control circuit is configured to generate a plurality of switching control signals for controlling the switching regulator circuit. The power supply circuit also includes a temperature sensitive circuit which includes a thermistor. The temperature sensitive circuit is configured to provide a variable voltage level output to the phase control circuit. The switching control circuit is also configured to suspend operation of the switching regulator circuit upon detecting a predetermined voltage level at the output.

Abstract: An indirect branch predictor includes a buffer storing branch target addresses corresponding to previously executed indirect branch instructions. The buffer is indexed with an index derived from history information corresponding to previously predicted indirect branch instructions and from the PC of the particular indirect branch instruction being predicted. In one embodiment, the buffer may be tagless and/or direct mapped. In various embodiments, the indirect branch target predictor may generate the index to the buffer using one or more techniques to improve the accuracy of the prediction: (i) offsetting the history information from the various previously predicted indirect branch instructions; (ii) weighting the history information based on the age of the previously predicted indirect branch instructions; and/or (iii) reversing the bit order of the PC of the particular indirect branch instruction being predicted.

Abstract: A method for controlling a process includes processing a first workpiece in a first process tool. An output characteristic of the first workpiece is measured. A second workpiece is processed in the first process tool. A tool health metric is determined for the first process tool corresponding to the processing of the second workpiece. A control action is determined based on the measured output characteristic and the tool health metric.

Abstract: A method of manufacturing a MOSFET semiconductor device comprises providing a gate electrode having first and second opposing sidewalls over a substrate having source/drain regions; providing a gate oxide between the gate electrode and the substrate; forming first and second sidewall spacers respectively disposed adjacent the first and second sidewalls; pre-cleaning the sidewall spacers; forming a nickel layer; and forming nickel silicide layers disposed on the source/drain regions and the gate electrode. The nickel silicide layers are formed during a rapid thermal anneal at temperatures from about 380 to 600° C. The pre-clean uses a hydrogen reactive system in an atmosphere comprising hydrogen and helium. Also, the pre-clean and the formation of the nickel layer are sequentially performed in a single physical vapor deposition chamber system.

Abstract: A method and apparatus for buffering data samples in a software-based ADSL modem. The method includes generating data for transmission to a remote source and modulating the data to form a plurality of data symbols for transmission. The data symbols are stored in a buffer. An absence of a data symbol in the buffer is determined. In response to detecting an absence of a data symbol in the buffer, an idle data symbol is transmitted.

Abstract: A Ta barrier slurry for Chemical-Mechanical Polishing (CMP) during copper metallization contains an organic additive which suppresses formation of precipitates and copper staining. The organic additive is chosen from a class of compounds which form multiple strong adsorbant bonds to the surface of silica or copper, which provide a high degree of surface coverage onto the reactive species, thereby occupying potential reaction sites, and which are sized to sterically hinder the collisions between two reactant molecules which result in new bond formation. The organic additive-containing slurry cain be utilized throughout the entire polish time. Alternatively, a slurry not containing the organic additive can be utilized for a first portion of the polish, and a slurry containing the organic additive or a polishing solution containing the organic additive can be utilized for a second portion of the polish.

Abstract: An indirect branch predictor includes a buffer storing branch target addresses corresponding to previously executed indirect branch instructions. The buffer is indexed with an index derived from history information corresponding to previously predicted indirect branch instructions and from the PC of the particular indirect branch instruction being predicted. In one embodiment, the buffer may be tagless and/or direct mapped. In various embodiments, the indirect branch target predictor may generate the index to the buffer using one or more techniques to improve the accuracy of the prediction: (i) offsetting the history information from the various previously predicted indirect branch instructions; (ii) weighting the history information based on the age of the previously predicted indirect branch instructions; and/or (iii) reversing the bit order of the PC of the particular indirect branch instruction being predicted.

Abstract: A novel method of providing an external host processor with access to registers located in different clock domains. The method comprises the steps of translating host processor interface signals into internal register interface signals, and performing handshaking with the registers via the internal register interface. The handshaking includes supplying registers with a register access signal for enabling access to a selected register, and producing a register ready signal in response to the register access signal. Synchronization signals delayed with respect to the register ready signal may be used for synchronizing registers located in different clock domains with the processor interface.

Abstract: A method comprises a “two-step” formation of a front side substrate contact in an FET formed over a buried insulator layer on a substrate, thereby avoiding the difficulties and problems involved in etching openings of high aspect ratio through a stack of different materials, as in a conventional front side substrate contact opening.

Abstract: One aspect of the invention relates to a virtual ground array floating gate flash memory device with salicided buried bit lines. The bit lines are implanted and salicided after formation of memory cell stacks, but before formation of word lines. The salicide can form over control gates for the memory cells and can contact a third poly layer from which the word lines are patterned. According to another aspect of the invention, an interpoly dielectric coats the sides of the floating gates and significantly improves the capacitance between the floating gate and the memory cell channel. The present invention provides very compact and reliable non-volatile memory.

Abstract: Multiple dopant implantations are performed on a FinFET device to thereby distribute the dopant in a substantially uniform manner along a vertical depth of the FinFET in the source/drain junction. Each of the multiple implantations may be performed at different tilt angles.

Abstract: A method of fabricating a semiconductor device. A first layer comprising a first material is deposited to a first thickness on a sidewall of a stacked gate. A second layer comprising a second material is deposited over the first layer. The second layer is deposited without the first layer being etched; hence, the first thickness is unchanged along the sidewall. The second layer is reduced to a second thickness along the sidewall. The first layer and the second layer in combination form a spacer along the sidewall that has a thickness corresponding to the first thickness and the second thickness. Thus, the spacer can be formed using a single etch, reducing the number of processing steps. In addition, the first layer protects shallow trench filler material from gouging during the etch.

Abstract: An apparatus is contemplated, including a router and a memory controller. The router is configured to route a write request and write data to the memory controller. The memory controller is coupled to receive the write request and the write data. If the write data is a number of bytes less than a minimum number of bytes writeable to a memory to which the memory controller is capable of being coupled, the memory controller is configured to read first data from the memory. The first data comprises the minimum number of bytes and includes bytes to be updated with the write data. The memory controller is configured to return the first data to the router as a read response. The router is configured to return the first data to the memory controller.

Abstract: The electromigration resistance of planarized metallization patterns, for example copper, inlaid in the surface of a layer of dielectric material, is enhanced by a process comprising blanket-depositing on the planarized, upper surfaces of the metallization features and the dielectric layer at least one alloying layer comprising at least one alloying element for the metal of the features, and diffusing the at least one alloying element within the metallization features to effect alloying therewith. The at least one alloying element diffused within the metallization features, under conditions wherein an oxide layer forms on the surface of the metallization features, forms a stable oxide layer on the surface of the metallization features. The stable oxide layer reduces electromigration from the metallization features along the oxide layer.

Abstract: A device and method for making a semiconductor-on-insulator (SOI) structure having a leaky, thermally conductive material (LTCIM) layer disposed between a semiconductor substrate and a semiconductor layer.

Abstract: For determining the quality of interconnections in integrated circuits, especially in damascene applications, a method of monitoring voids is disclosed, wherein a barrier metal layer is directly deposited on a planarized metal to provide a large-area surface that is not required to be destroyed for further analysis of the interface between the metal and the barrier metal layer. The analysis may be carried out by employing an electron microscope operated in a back-scatter mode.

Abstract: A method of processing a semiconductor device is disclosed and comprises applying a relatively high voltage across a gate stack of a flash memory cell for a certain period of time. Then, the polarity of the applied voltage is reversed and is again applied across the gate stack for another certain period of time. The voltage applied is greater than a channel erase voltage utilized for the memory cell. This applied voltage causes extrinsic defects to become amplified at interfaces of oxide/insulator layers of the gate stack. Then, the memory cell is tested (e.g., via a battery of tests) in order to determine if the memory cell is defective. If the cell is defective (e.g., fails the test), it can be assumed that substantial extrinsic defects were present in the memory cell and have been amplified resulting in the test failure. If the cell passes the test, it can be assumed that the memory cell is substantially free from extrinsic defects.

Abstract: A process for forming sub-lithographic features in an integrated circuit is disclosed herein. The process includes modifying a photoresist layer after patterning and development but before it is utilized to pattern the underlying layers. The modified photoresist layer has different etch rates in the vertical and horizontal directions. The modified photoresist layer is trimmed with a plasma etch. A feature included in the trimmed photoresist layer has a sub-lithographic lateral dimension.

Abstract: A method of reducing electromigration in a dual-inlaid copper interconnect line (3) by filling a via (6) with a Cu-rich Cu—Zn alloy (30) electroplated on a Cu surface (200 from a stable chemical solution, and by controlling the Zn-doping thereof, which also improves interconnect reliability and corrosion resistance, and a semiconductor device thereby formed. The method involves using a reduced-oxygen Cu—Zn alloy as fill (30) for the via (6) in forming the dual-inlaid interconnect structure (35). The alloy fill (30) is formed by electroplating the Cu surface (20) in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants, thereby electroplating the fill (30) on the Cu surface (20); and annealing the electroplated Cu—Zn alloy fill (30); and planarizing the Cu—Zn alloy fill (30), thereby forming the dual-inlaid copper interconnect line (35).