Abstract: A network repeater having a plurality of repeater ports selectively establishes links with remote nodes at one of two data rates based on the capabilities of the remote network node, configuration information supplied by user in circuitry, and a determined link integrity. A network repeater establishes a link with a network node using auto-negotiation techniques to establish a 100 Mb/s link. The network repeater than monitors the link for symbol errors, and determines an integrity of the link based on a detected number of symbol errors relative to a prescribed threshold in a dual-counter configuration. If the detected number of symbol errors counted by the first counter within a first number of received symbols, the second counter is incremented and the first counter reset. If over a second, longer interval the second counter reaches a second threshold reaches the prescribed threshold, indicating poor link integrity due to poor cable connection or condition, faulty network device, etc.

Abstract: A proxy device such as a microcontroller, coupled to the SMBus, is configured for obtaining, according to the SMBus Address Resolution Protocol (ARP) and from an Address Resolution Protocol (ARP) master, an SMBus slave address for an SMBus device. The proxy device also is configured for outputting the obtained SMBus slave address for storage by the SMBus device independent of the ARP protocol. Hence, the proxy agent enables SMBus slave addresses to be assigned in SMBus devices that lack the ability to receive an assigned SMBus address according to the SMBus ARP.

Abstract: A tagging and arbitration mechanism in an input/output node of a computer system. A mechanism for tagging commands in an input/output node of a computer system includes a tag circuit configured to receive a plurality of control commands. The tag circuit may also be configured to generate a tag value for each of the control commands. The tagging mechanism may also include a buffer circuit which is coupled to the tag circuit. The buffer circuit may include a plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels for storing selected control commands that belong to the respective virtual channel. Further the tagging mechanism may include an arbitration circuit that is coupled to the buffer circuit and is configured to arbitrate between the plurality of buffers depending upon the tag value for each of the control commands.

Abstract: A network switch, configured for performing layer 2 and layer 3 switching in an Ethernet (IEEE 802.3) network without blocking of incoming data packets, includes network switch ports, each including a port filter configured for obtaining and filtering relevant layer 2 and layer 3 information from a received layer 2 frame. Each port filter, upon filtering the relevant layer 2 and layer 3 information from a received layer 2 frame, outputs the relevant layer 2 and layer 3 information to switching logic, enabling the switching logic to perform layer 3 processing to determine a layer 3 switching operation to be performed on the received layer 2 frame. Hence, the switching logic performs the layer 3 processing based on the relevant layer 2 and layer 3 information, without the necessity of parsing the received layer 2 and layer 3 information by the switching logic.

Abstract: A method and system for insulating a lower layer of a semiconductor device from an upper layer of the semiconductor device is disclosed. The method and system include providing an interlayer dielectric on the lower layer. The method and system further include providing an antireflective coating (ARC) layer. At least a portion of the ARC layer is on the interlayer dielectric. The method and system further include providing a plurality of via holes in the interlayer dielectric and the ARC layer and filling the plurality of via holes with a conductive material. The method and system further include removing the ARC layer while reducing subsequent undesirable charge gain and subsequent undesirable charge loss over the use of a chemical mechanical polish in removing the ARC layer.

Abstract: A method is provided, the method including forming a gate dielectric above a substrate layer, and forming a gate conductor above the gate dielectric. The method also includes forming at least one dielectric isolation structure in the substrate adjacent the gate dielectric.

Abstract: A metal gate electrode is formed with an intrinsic electric field to modify its work function and the threshold voltage of the transistor. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing one or more layers of tantalum nitride such that the nitrogen content increases from the bottom of the layer adjacent the gate dielectric layer upwardly. Other embodiments include forming the intrinsic electric field to control the work function by doping one or more metal layers and forming metal alloys. Embodiments further include the use of barrier layers when forming metal gate electrodes.

Abstract: A method of making a Silicon-on-Insulator (SOI) transistor includes forming a body layer that is fully depleted when the SOI transistor is in a conductive state and forming first p+ regions adjacent each of the SOI transistor source/drain regions to adjust the SOI transistor threshold voltage. To suppress punch-through current, an additional implant step is carried out to form second p+ regions adjacent first implant regions.

Abstract: A method and system for providing a semiconductor device is disclosed. The method and system include providing a semiconductor substrate and providing a plurality of lines separated by a plurality of spaces. Each of the plurality of spaces preferably has a first width that is less than a minimum feature size. In one aspect, the method and system include providing a reverse mask having a plurality of apertures on an insulating layer. In this aspect, the method and system also include trimming the reverse mask to increase a size of each of the plurality of apertures, removing a portion of the insulating layer exposed by the plurality of trimmed apertures to provide a plurality of trenches and providing a plurality of lines in the plurality of trenches. In a second aspect, the method and system include providing a reverse mask on the insulating layer and removing a first portion of the insulating layer exposed by the plurality of apertures to provide a plurality of trenches.

Abstract: A system for regulating gate oxide layer formation is provided. The system includes one or more light sources, each light source directing light to one or more gate oxide layers being deposited and/or formed on a wafer. Light reflected from the gate oxide layers is collected by a measuring system, which processes the collected light. The collected light is indicative of the thickness and/or uniformity of the respective gate oxide layers on the wafer. The measuring system provides thickness and/or uniformity related data to a processor that determines the thickness and/or uniformity of the respective gate oxide layers on the wafer. The system also includes a plurality of gate oxide layer formers where each gate oxide former corresponds to a respective portion of the wafer and provides for gate oxide layer formation thereon. The processor selectively controls the gate oxide layer formers to regulate gate oxide layer formation on the respective gate oxide layer formations on the wafer.

Abstract: A structure and an improved isolation trench between active regions within the semiconductor substrate involves forming on a silicon substrate and forming a nitride layer on the pad layer. Thereafter, a photoresist layer is patterned on the silicon nitride layer such that regions of the nitride layer are exposed where an isolation trench will subsequently be formed. Next, the exposed regions of the nitride layer and the pad layer situated below the exposed regions of the nitride layer are etched away to expose regions of the silicon substrate. Subsequently, isolation trenches are etched into the silicon substrate with a dry etch process. A trench liner is then formed and nitrogen incorporated into a portion of the trench liner to form an oxynitride layer. After formation of the oxynitride layer, the trench is filled with a dielectric preferably comprised of a CVD oxide. Thereafter, the CVD fill dielectric is planarized and the nitride layer is stripped away.

Abstract: A method of programming a memory device having a plurality of pages of memory. The method includes programming the memory, monitoring the memory for defects, creating a copy of the data, erasing the old version of the data, and rewriting the data. The first page of memory is programmed with a first data set. The first page of memory is monitored for errors. During the monitoring for errors, some detected errors may be corrected. When the number of errors detected exceeds a threshold, a copy of that page of memory is created. The number of errors detected can be a fixed number a percentage of the memory, or time dependent. The copy can be created in an other page of local memory of in remote memory. Then the first page of memory is erased. Finally, the first data set rewritten.

Abstract: A cache controller configured to speculatively invalidate a cache line may respond to an invalidating request or instruction immediately instead of waiting for error checking to complete. In case the error checking determines that the invalidation is erroneous and thus should not be performed, the cache controller protects the speculatively invalidated cache line from modification until error checking is complete. This way, if the invalidation is later found to be erroneous, the speculative invalidation can be reversed. If error checking completes without detecting any errors, the speculative invalidation becomes non-speculative.

Abstract: A method for processing an interrupted workpiece includes providing a dynamic control model defining the processing characteristics of a processing tool throughout a processing run; providing a partially processed workpiece; determining an extent of processing metric for the partially processed workpiece; and determining at least one operating recipe parameter of the processing tool based on the dynamic control model and the extent of processing metric. A manufacturing system includes a processing tool and a process controller. The processing tool is adapted to process a partially processed workpiece in accordance with an operating recipe. The process controller is adapted to determine an extent of processing metric for the partially processed workpiece and determine at least one parameter of the operating recipe based on a dynamic control model defining the processing characteristics of the processing tool throughout a processing run and the extent of processing metric.

Abstract: A methodology for testing interconnect structures includes testing a number of short line interconnects having the same length and different reservoir sizes. By measuring and comparing the stress values on the interconnects, a relationship between reservoir area and jLcrit may be obtained. This information may then be used to more accurately assess the reliability of an interconnect and to design more reliable interconnects.

Abstract: Gate oxide surface irregularities, such as surface roughness, are reduced by treatment with an oxygen-containing plasma. Embodiments include forming a gate oxide layer and then treating the formed gate oxide layer with an oxygen plasma to repair weak spots and fill in pin holes and surface irregularities, thereby reducing gate/gate oxide interface roughness.

Abstract: A MOSFET semiconductor device includes a substrate, a gate electrode, a gate oxide, first and second sidewall spacers, and nickel silicide layers. The gate oxide is disposed between the gate electrode and the substrate, and the substrate includes source/drain regions. The gate electrode has first and second opposing sidewalls, and the first and second sidewall spacers are respectively disposed adjacent the first and second sidewalls. The first and second sidewall spacers are formed from a low-K spacer material that is substantially non-reactive with nickel, for example, SiHC, hydrogen silsesquioxane and methyl silsesquioxane. The nickel silicide layers are disposed on the source/drain regions and the gate electrode. A method of manufacturing the semiconductor device is also disclosed.

Abstract: A method and apparatus are provided for controllably dispensing flux on a substrate having a plurality of conductive terminals. Flux having a viscosity range between 10 centipoises and about 150 centipoises is sprayed on the substrate and the conductive terminals at a valve pressure range between about 1.5 psi and about 30 psi via a dispense nozzle of a flux dispenser. Upon a subsequent high temperature solder reflow process, the sprayed flux on the substrate is mostly removed by thermal decomposition to volatile species, thereby significantly reducing flux residue remaining on the surface of the substrate between the conductive terminals.

Abstract: A system and method are provided for calculating a plurality of bottleneck delta virtual work in process time (“VWIP”) values. Each of the bottleneck delta VWIP values represents the time until one of n bottleneck workstations begins to risk starvation. The calculating includes deriving one or more baseline cycle times based on an X-factors method.

Abstract: Post-manufacturing analysis of a semiconductor chip is enhanced via a method and system for viewing emissions through substrate in the back side of the chip. According to an example embodiment of the present invention, a portion of circuitry in a semiconductor chip is excited, and an emission is generated. An optical microscope is directed at the backside of the chip, and an image of the emission is obtained. The optical microscope is coupled to an indium-gallium-arsenic (InGaAs) camera that is used to detect the emission. In this manner, emissions can be detected through substrate in a semiconductor chip.