Abstract: For fabricating a shallow trench isolation structure, a notched masking structure is formed over an active area of a semiconductor substrate. A shallow trench opening is formed at a side of the active area with a top corner of the shallow trench opening being exposed and facing a notched surface of the notched masking structure. Liner oxide is formed in a thermal oxidation process at the top corner of the shallow trench opening to round the top corner of the shallow trench opening. The liner oxide may also be formed on walls including the bottom corner of the shallow trench opening during the thermal oxidation process. The shallow trench opening is then filled with a trench dielectric material to form the shallow trench isolation structure.

Abstract: A method of manufacturing a MOSFET semiconductor device includes forming a gate electrode oxide over a substrate; depositing a first layer of polysilicon over the gate oxide; implanting dopants in the first layer; depositing a second layer of polysilicon over the first layer; etching both layers to form a gate electrode; forming source/drain extensions in the substrate; forming first and second sidewall spacers; implanting dopants within the substrate to form source/drain regions in the substrate; and laser thermal annealing to activate the source/drain regions and to melt the first layer. The first layer can have a depth of about 200 to 500 angstroms, and the second layer can have a depth of about 300 to 4500 angstroms. The source/drain extensions can have a depth of about 50 to 300 angstroms, and the source/drain regions can have a depth of about 400 to 1000 angstroms. The laser thermal annealing can also melt amorphitized portions of the second layer.

Abstract: A method for forming a group of structures in a semiconductor device includes forming a conductive layer on a substrate, where the conductive layer includes a conductive material, and forming an oxide layer over the conductive layer. The method further includes etching at least one opening in the oxide layer, filling the at least one opening with the conductive material, etching the conductive material to form spacers along sidewalls of the at least one opening, and removing the oxide layer and a portion of the conductive layer to form the group of structures.

Abstract: In one illustrative embodiment, a method is provided that controls a stepper to position a focal plane of a light source adjacent a top surface of a layer of photoresist. A metrology tool is used to measure a thickness of the layer of photoresist, and a controller uses the thickness measurement to determine a position of the top surface of the layer of photoresist. The controller delivers a control signal to the stepper, causing the stepper to move the focal plane of the light source adjacent the top surface of the layer of photoresist.

Abstract: A method and related system for transferring data between systems having different clock domains. A skip signal generation circuit calculates substantially simultaneously with the transfer of data which signals of the faster clock domain should be skipped to ensure proper operation. The skip signal generation circuit makes this determination using values representing the faster and slower frequencies of each clock domain. These values are obtained either from preset values integrated in some form onto the microprocessor substrate, or may be written to the microprocessor by external circuitry and software. The skip signal generation circuit is capable of calculating skip patterns for any ratio of faster to slower frequency and is not constrained to have integer or half-integer ratios of the faster and slower clock domains.

Abstract: A method of forming a specialized channel region removes a sacrificial gate material and provides a semiconductor implant though the recess associated with the remove sacrificial gate material. The process can be utilized to form a silicon germanium layer in the channel region having a sharp profile in the vertical direction. Further, the silicon germanium layer can be ultra-thin. The silicon germanium channel region has increased charge mobility with respect to conventional channel regions.

Abstract: Transient signals resulting from format changes in a signal processing circuit that cause audible popping and clicking noises are simply and efficiently eliminated by disabling handling of data samples during changes between data formats. The transient signals are eliminated in a signal processor circuit that includes a buffer for storing digital data samples and a circuit for eliminating format-dependent transients in a signal processor connected to the buffer. The digital data samples are selectively formatted in a plurality of data formats. The circuit for eliminating format-dependent transients includes a sample formatter connected to the buffer that receives digital data samples from the buffer and selectively modifies the digital data samples from a first data format to a second data format of the plurality of data formats.

Abstract: A network switching system having a plurality of multiport switch modules arranged in a cascaded sequence uses a signaling protocol that eliminates the necessity of storing a given network address within each of the address forwarding tables of the multiport switch modules. A network switch module, having an address forwarding table for storing switching information for respective stored network addresses and that receives a data packet, outputs a switching request to a subsequent one of the switch modules based on a determined absence of the destination address of the received data packet in the address forwarding table. Each of the successive network switch modules passes the switching request to the next switch module in the sequence upon a determined absence of the destination address in the corresponding address forwarding table.

Abstract: A manufacturing method for a MirrorBit® Flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. The hard mask is of a material formulated for removal without damaging the charge-trapping dielectric layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A salicide is grown without short-circuiting the first and second bitlines.

Abstract: The introduction of alloying elements into a metal conductive element is achieved in situ in conjunction with a post-CMP reducing treatment. The source of the alloying elements may be a source gas introduced into the plasma chamber, or a source material incorporated into a post-CMP residue through presence in a CMP slurry or a post-CMP rinsing agent, or applied to the substrate prior to plasma treatment. The alloying element is introduced into the metal conductive element by diffusion during plasma treatment.

Abstract: A method and an apparatus for performing a process control using partial measurement data. A process operation is performed on a semiconductor wafer. Inline metrology data related to the process of the semiconductor wafer is acquired. A partial measurement data acquisition process is performed based upon the inline metrology data, the partial measurement data acquisition process comprising determining a time period for acquiring the inline metrology data, determining a number of wafers to be sampled based upon the time period, and determining a number of wafer sites for data acquisition. At least one of a feedback adjustment on a second semiconductor wafer and a feed-forward adjustment relating to a subsequent processing of the first semiconductor wafer based upon the partial measurement data acquisition process is performed.

Abstract: A first package for an integrated circuit has both a first set of electrical contacts and a first connector. A second package has a second set of electrical contacts and a second connector. The first and the second connector are mating connectors that are electrically and physically coupled. The first set of electrical contacts and the first connector are disposed on opposite surfaces of the first package and the second set of electrical contacts and the second connector are disposed on the same surface of the second package. The first and second set of electrical contacts couple to a printed circuit board directly or indirectly through a socket. The connectors allow higher speed signals to be routed over the first and second connectors, while power, ground and slower speed signals can be routed over the first set and second set of electrical contacts.

Abstract: A silicon-on-insulator(SOI) transistor. The SOI transistor having a source and a drain having a body disposed therebetween, the source being implanted with germanium to form an area of silicon-germanium adjacent a source/body junction in a lower portion of the source, the area of silicon-germanium in the source forming a hereto junction along a lower portion of the source/body junction.

Abstract: A processing system includes a sensor, a processing tool, and an automatic process controller. The sensor has a plurality of sensing regions. The processing tool is adapted to process at least one process layer on a wafer. The process tool includes a process control device controllable by a process control variable. The sensor is adapted to measure a process layer characteristic of the process layer in a selected one of the sensing regions. The automatic process controller is adapted to receive the process layer characteristics measured by the sensor and adjust the process control variable in response to the process layer characteristic measured in one sensing region differing from the process layer characteristic measured in another sensing region.

Abstract: For generating a margining voltage for biasing a gate of a CAM (content addressable memory) cell of a flash memory device fabricated on a semiconductor wafer, a high voltage source is provided with a voltage generator fabricated on the semiconductor wafer. A low voltage source is provided from a node coupled to the voltage generator fabricated on the semiconductor wafer. For example, the voltage generator for providing the high voltage source includes a voltage regulator and a charge pump fabricated on the semiconductor wafer, and the low voltage source is the ground node. In addition, a first transistor is coupled to the high voltage source, and a second transistor is coupled to the low voltage source. A first resistor is coupled between the first transistor and an output node, and a second resistor coupled between the second transistor and the output node. The margining voltage is generated at the output node.

Abstract: The density of a deposited silicon nitride layer is increased by laser thermal annealing in N2, thereby increasing etch selectivity with respect to an overlying oxide and, hence, avoiding damage to underlying silicide layers and gates. Embodiments include laser thermal annealing a silicon nitride layer deposited as an etch stop layer, e.g., in fabricating EEPROMs, to increase its density by up to about 8%, thereby increasing its etch selectivity with respect to an overlying BPSG layer to about {fraction (1/12)} to about {fraction (1/14)}.

Abstract: A method of defining a toleranced process based on a nominal process, applicable to any manufacturing process wherein the output is dependent on a process having a number of input factors which are subject to variation, and have a mean and standard deviation. The method comprises the steps of: representing the variability of the response of a system to the actual distribution of at least one of said factors and parameterized by at least one parameter; performing at least one step in the manufacturing process for a given lot of wafers; evaluating actual variability and nominal variability of said components against a schedule of parameters in an array; modeling the output of the evaluation to determine the manner in which to continue processing of the lot.

Abstract: A method of forming multiple structures in a semiconductor device includes depositing a film over a conductive layer, etching a trench in a portion of the film and forming adjacent the sidewalls of the trench. The film may then be etched, followed by an of the conductive layer to form the structures.

Abstract: A semiconductor device is provided with the high-speed capabilities of silicon on insulator (SOI) and strained silicon technologies, without requiring the formation of a silicon germanium layer. A layer of compressive material is formed on a SOI semiconductor substrate to induce strain in the overlying silicon layer. The compressive materials include silicon oxynitride, phosphorous, silicon nitride, and boron/phosphorous doped silica glass.

Abstract: Several methods for providing an estimate of the current time are described for use in a computer system including a local time source (e.g., a real time clock or RTC). The local time source is capable of holding one of multiple levels of trust with regard to timekeeping, where the levels of trust are ranked with respect to one another. The level of trust of the local time source is dependent upon a timekeeping accuracy of the local time source. The level of trust of the local time source may also be dependent upon a timekeeping stability, a timekeeping reliability, and/or a timekeeping security (e.g., a tamper resistance) of the local time source.