Abstract: A self-aligned semiconductor interconnect barrier between channels and vias is provided which is self-aligned and made of a metallic barrier material. A channel is conventionally formed in the semiconductor dielectric, lined with a first metallic barrier material, and filled with a conductive material. A recess is etched to a predetermined depth into the conductive material, and the second metallic barrier material is deposited and removed outside the channel. This leaves the conductive material totally enclosed in metallic barrier material. The metallic barrier material is selected from metals such as tantalum, titanium, tungsten, compounds thereof, alloys thereof, and combinations thereof.

Abstract: A method for removing unwanted header information from a frame in a network is disclosed. It includes: storing beginning bytes of the frame in a first buffer and remaining bytes in a second buffer, where a size of the first buffer is smaller than the second buffer; determining that the unwanted header information is stored in the first buffer; copying bytes of the frame after the unwanted header information that are stored in the first buffer over the unwanted header information; reporting a number of bytes of the frame stored in the first buffer to be retrieved; and retrieving the reported number of bytes of the frame stored in the first buffer and the bytes of the frame stored in the second buffer. The copying of bytes occurs exclusively in the first buffer. Thus, removing the unwanted header information requires fewer processor cycles and minimizes latency in the packet receive process.

Abstract: The present invention is directed to a method of controlling an etching process used to form a gate electrode on a semiconductor device. In one embodiment, the method comprises forming a layer of silicon dioxide above a semiconducting substrate, and forming a layer of polysilicon above the layer of silicon dioxide. The method further comprises sensing a thickness of the layer of polysilicon and adjusting, based upon the sensed thickness of said layer of polysilicon, at least one parameter of an etching process to be performed on said layer of polysilicon to define a gate electrode of a transistor, said etching process comprised of at least a timed etch process and an endpoint etch process.

Abstract: A semiconductor isolation material deposition system and method that facilitates convenient and efficient integrated multi-step deposition of isolation regions is presented. In one embodiment of the present invention, an integrated circuit includes densely configured component areas and sparsely configured component areas. An active area in a wafer is created and a shallow trench space is formed. A thin layer of TEOS isolation material layer is deposited on top of the active area and the shallow trench. For example, the layer of thin layer of TEOS isolation material is in a range of 4000 to 5000 angstroms thick over the top of underlying active areas. A reverse mask and pre-planarization etch is performed on the thin layer of TEOS isolation material. The remaining TEOS edge spikes between the densely configured component area and the sparsely configured component area are minimal (e.g., about 500 angstroms.

Abstract: A method and apparatus for testing semiconductors comprising shallow trench isolation (STI) edge structures. An edge intensive shallow trench isolation structure (500) is coupled to a voltage source (310) and a current versus voltage profile is recorded. A planar structure (600) on the same wafer is coupled to a voltage source and a current versus voltage profile is recorded. An electrical stress is applied to both structures. Additional current profiles of each structure are obtained after the electrical stress. A comparison of difference current profiles obtained for the two types of structures may indicate the presence and/or the extent of STI corner effects. More specifically, a value for a normalized gate current difference for an STI edge intensive structure (500) greater than normalized gate current difference of a planar structure (600) is indicative of an increased rate of electron trapping in STI corners, which may indicate that the STI corners are too thin.

Abstract: A method of programming a memory unit having a plurality of dual cell core memory devices and at least one dual cell dynamic reference device. The memory unit is subjected to an erase configuration operation such that each cell of the core memory devices is in a blank state and such that a threshold voltage of the at least one dynamic reference device is less than a charged program level threshold voltage. Thereafter, the at least one dynamic reference and the core memory devices are programmed using a page programming routine.

Abstract: A dual bit dielectric memory cell comprises a substrate with a source region and a drain region implanted on opposing sides of a central channel region. A multilevel charge trapping dielectric is positioned on the substrate above the central channel region and includes a central region between an opposing source lateral region and a drain lateral region. A control gate is positioned above the multilevel charge trapping dielectric. The multilevel charge trapping dielectric comprises a tunnel dielectric layer adjacent the substrate, a top dielectric adjacent the control gate, and a charge trapping dielectric positioned there between. The thickness of the tunnel dielectric layer in the central region is greater than a thickness of the tunnel dielectric layer in each of the source lateral region and the drain lateral region.

Abstract: Direct sequence spread spectrum encoder and method for digital information in wireless LANs are provided. The encoder comprises a spreading means for mapping two input data bits to one sequence out of four selectable, nearly orthogonal sequences being selected from 216 possible sequences. The encoder further comprises a digital-to-analog converter connected to an output of the spreading means for generating an analog signal based on the symbols as outputted by the spreading means and a low-pass filter connected to an output of the digital-to-analog converter for low-pass filtering the analog signal.

Abstract: A strained silicon layer is grown on a layer of silicon germanium and a second layer of silicon germanium is grown on the layer of strained silicon in a single continuous in situ deposition process. Both layers of silicon germanium may be grown in situ with the strained silicon. This construction effectively provides dual substrates at both sides of the strained silicon layer to support the tensile strain of the strained silicon layer and to resist the formation of misfit dislocations that may be induced by temperature changes during processing. Consequently the critical thickness of strained silicon that can be grown on substrates having a given germanium content is effectively doubled. The silicon germanium layer overlying the strained silicon layer may be maintained during MOSFET processing to resist creation of misfit dislocations in the strained silicon layer up to the time of formation of gate insulating material.

Abstract: A timing error correction technique for use in data communications receivers such as WLAN (Wireless Local Area Network) receivers is provided where an input signal is received that has a timing error, the timing error is corrected, and a signal having a corrected timing error is output. The timing error correction comprises performing an early-late correlation on the signal that has the corrected timing error. The early-late correlation comprises the generation of at least one early and late sample pair, the generation of an error signal that is indicative of the difference between the early and late samples, and the generation of at least one control signal based on the error signal. A time offset correction algorithm is performed dependent on the control signal.

Abstract: An improved data communication receiver technique is provided which avoids demodulation errors due to abrupt phase changes. A receiver is provided for processing an incoming digitized signal. The receiver comprises a pre-processing portion, a phase error correction unit and a signal evaluation unit. The pre-processing portion is adapted to process the digitized signal for providing a non-coherent pre-processed signal. The phase error correction unit is adapted to correct a phase error of the non-coherent pre-processed signal and output a coherent signal. The signal evaluation unit is adapted to extract information from the non-coherent pre-processed signal and to output a data signal representing the extracted information. The phase error correction unit and said signal evaluation unit are configured to operate simultaneously for a predetermined time.

Abstract: A complementary code decoder technique is provided where the encoded input data is first parallelized. From the parallelized data, correlation values are generated by a correlator circuit that is capable of changing its correlation characteristics depending on at least one control signal. Different control signals are sequentially provided to the correlator circuit thereby driving the correlator circuit to sequentially generate multiple correlation values from the parallelized data, based on different correlation characteristics. From the multiple correlation values, the correlation value that represents the optimum correlation is identified. This technique significantly reduces the gate count of the decoder structure, thus saving chip area and manufacturing costs.

Abstract: An improved decision feedback equalization technique is provided that may be used in data communications receivers such as those in WLAN (Wireless Local Area Network) systems. The decision feedback equalizer comprises a feedforward filter that is connected to receive an input data signal and output a filter representation thereof. The feedforward filter has a filter characteristic that depends on filter coefficient data. The decision feedback equalizer further comprises a filter coefficient computation unit for generating the filter coefficient data and outputting the generated data to the feedforward filter. At least one data processing circuit is provided that receives a mode switch signal for switching its operational mode. The data processing circuit is arranged for performing a feedforward filter function in one operational mode and a filter coefficient computation function in another operational mode.

Abstract: A WLAN (Wireless Local Area Network) transmitter or another data communications apparatus is provided that comprise a transmission section that is configured to generate signals to be transmitted, and a control section that is connected to the transmission section to control the transmission section dependent on at least two transmission parameters. The control section comprises a state transition controller that is configured to step through a plurality of predefined control states. The control section is configured to apply different transmission parameter modification mechanisms in different control states. The state transition controller is configured to determine the respective next control states based on transmission success and failure statistics.

Abstract: A network switch having switch ports for communication of data packets with respective computer network nodes according to CSMA/CD protocol that resets a retry counter within any one of the respective switch ports if backpressure is asserted by that port. The resetting of the retry counter within a port after assertion of backpressure affords the port a greater probability of winning collision mediation under the CSMA/CD protocol, thus more quickly relieving congestion which may occur in the network switch.

Abstract: A non-destructive and non-intrusive, user friendly, easy to setup and efficient system and method of determining the gate oxide thickness of an operational MOSFET used in real circuit applications is provided. Additionally, the present invention determines the gate oxide thickness when the operational MOSFET is operating in the inversion mode.

Abstract: A memory circuit arrangement for sensing current in a target cell during a read operation is disclosed. According to one exemplary embodiment, the memory circuit arrangement comprises the target cell and a first neighboring cell adjacent to the target cell. The first target cell has a first bit line connected to ground; the target cell also has a second bit line connected to a sensing circuit. The first neighboring cell shares the second bit line with the target cell; the first neighboring cell also has a third bit line connected to the sensing circuit during the read operation. The memory circuit arrangement results in increased error margins in a fast and accurate manner during the read operation of the target cell.

Abstract: A semiconductor device and method of making the same includes a first metallization level, a first etch stop layer, a dielectric layer and an opening extending through the dielectric layer and the first etch stop layer. The first etch stop layer is disposed over the first metallization level. Metal within the opening forms a second metal feature, and the metal can comprise copper or a copper alloy. Dopants are introduced into the metal and are activated by laser thermal annealing. A concentration of the dopants within the metal in a lower portion of the second metal feature proximate the first metal feature is greater than a concentration of dopants in a central portion of the second metal feature, and a concentration of the dopants within the metal in an upper portion of the second metal feature is greater than a concentration of dopants in the central portion of the second metal feature.

Abstract: In protecting Flash memory data, a flexible system and method provides for different levels of protection. It offers the ability to dynamically lock a sector of memory using a dynamic protection bit in volatile memory. It offers persistent locking of a sector using a non-volatile bit in memory and locking this status using a lock bit in volatile memory. It offers yet further protection by including a password mode which requires a password to clear the lock bit. The password is located in an unreadable, one time programmable area of the memory. The memory also includes areas, whose protection state is controlled by an input signal, for storing boot code in a protected manner.

Abstract: A switching system includes a multiport module having an address table for storing network addresses, and a host processor configured for selectively swapping the stored network addresses in the address table to an internal memory that serves as an overflow address table for the multiport switch module. The address table internal to the multiport module is configured for storing a prescribed number of network addresses for high-speed access, for example the most frequently-used network addresses. The host processor, configured for controlling the storage of network addresses between the address table and the external memory, uses the external memory as the overflow address table for storage of less frequently-used network addresses, for example addresses of network devices that transmit little more than periodic “keep-alive” frames. Hence, a large number of addresses may be managed by the switching system, without the necessity of an unusually large on-chip address table.