Patents Assigned to Advanced Micro Devices, Inc.
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Patent number: 6716646Abstract: The present invention provides for a method and an apparatus for overlay measurements using optical techniques. At least one semiconductor device is processed. Metrology data from the processed semiconductor device is acquired. A scatterometry overlay analysis based upon the metrology data is performed. At least one modified manufacturing parameter is calculated based upon the scatterometry overlay analysis.Type: GrantFiled: July 16, 2001Date of Patent: April 6, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Marilyn I. Wright, Kevin R. Lensing, James Broc Stirton, Richard J. Markle
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Patent number: 6716684Abstract: A self-aligned transistor and method making a self-aligned transistor, the transistor including a first silicon portion on an isolation layer, the silicon portion having formed therein a source region and a drain region separated by a channel region. The channel region has a first side and a second side and a top portion, and a gate oxide surrounds the channel on said first side, second side and top portion. A first, a second and a third silicon gate regions are positioned in a second silicon portion surrounding the first silicon portion about the first side, second side and top portion and the channel region.Type: GrantFiled: November 13, 2000Date of Patent: April 6, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Zoran Krivokapic, Matthew Buynoski
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Patent number: 6716686Abstract: A method for forming one or more FinFET devices includes forming a source region and a drain region in an oxide layer, where the oxide layer is disposed on a substrate, and etching the oxide layer between the source region and the drain region to form a group of oxide walls and channels for a first device. The method further includes depositing a connector material over the oxide walls and channels for the first device, forming a gate mask for the first device, removing the connector material from the channels, depositing channel material in the channels for the first device, forming a gate dielectric for first device over the channels, depositing a gate material over the gate dielectric for the first device, and patterning and etching the gate material to form at least one gate electrode for the first device.Type: GrantFiled: July 8, 2003Date of Patent: April 6, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Matthew S. Buynoski, Judy Xilin An, Bin Yu
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Patent number: 6718379Abstract: A centralized policy server sends policy messages, that describe network management policy, to network switches. Each policy message includes a packet attribute that enables a network switch to uniquely identify a received data packet, and either a priority level or network switch action that describes the switching operation to be performed by the network switch. The network switches are configured for implementing the network management policy by storing switching actions for prescribed data packets, and templates that specify frame data parameters for identifying the prescribed data packets. Each network switch, configured for performing layer 2 and layer 3 switching in an Ethernet (IEEE 802.3) network without blocking of incoming data packets, includes in each network switch port a packet classifier module configured for classifying a received data packet based on a template generated based on the policy messages.Type: GrantFiled: June 9, 2000Date of Patent: April 6, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Gopal S. Krishna, Peter Ka-Fai Chow, Somnath Viswanath, Shr-Jie Tzeng, Mrudula Kanuri
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Patent number: 6718356Abstract: The invention relates generally to radix-r FFTs (Fast Fourier Transforms), and more particularly to a method and an apparatus for assigning data samples to memory when computing a radix-r FFT. In one embodiment, the apparatus comprises a plurality of memory banks for storing the data samples, a memory bank counter indicating the memory banks, a data sample counter for counting an increment of the data samples, a region difference counter for counting a region difference change of a butterfly stage, a computer program having the current values of the data sample counter and the region difference counter as input values for determining whether the fractional part of the current data sample value divided by the current region difference value equals zero, and a multiplexer for multiplexing the current data sample to an assigned memory bank if the fractional part is not equal zero.Type: GrantFiled: June 16, 2000Date of Patent: April 6, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Stephan Rosner, Frank Barth
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Patent number: 6716706Abstract: The present invention is a method of forming a channel device. The method comprises the steps of providing at least one active region on a substrate wherein the active region comprises a plurality of discontinuous gate structures. The method further comprises providing an ion implantation in the substrate. In accordance with the present invention, a higher Early Voltage is achieved thereby enabling halo/pocket and LDD implants to be effectively utilized in the design of analog circuitry.Type: GrantFiled: June 12, 2000Date of Patent: April 6, 2004Assignee: Advanced Micro Devices, Inc.Inventor: Zoran Krivokapic
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Patent number: 6717941Abstract: A method and apparatus for the early termination or deletion of frame data that is being transmitted or is scheduled for transmission from one network station to another network station. A network interface in the transmitting network station is able to read and transmit frame data as a central processing unit in the transmitting network is writing frame data into memory. The network interface reads a descriptor associated with frame data to determine if the frame data, which is either being transmitted or is scheduled for transmission, has a termination field indicating that the frame data is to be deleted. A descriptor management unit in the network interface reads the termination field in the descriptor and determines whether the frame data is currently being sent or is scheduled for transmission. If the frame data is scheduled for transmission, then the frame data is flushed from the data memory of the transmitting network station.Type: GrantFiled: February 2, 2000Date of Patent: April 6, 2004Assignee: Advanced Micro Devices, Inc.Inventor: Jeffrey Dwork
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Patent number: 6716702Abstract: A flash memory structure and its fabrication process, whereby stacks, of a first poly-crystalline silicon material or an amorphous silicon material (polysilicon), are processed for formation of a pre-interpoly dielectric treatment layer over the first polysilicon material. The pre-interpoly dielectric treatment layer being a solid material formed by a chemical reaction formed for purposes of improving the reliability of an interpoly dielectric member and results in changing the capacitor coupling ratio of the flash memory element and allows the use of new power supply and programming voltages. The pre-interpoly dielectric treatment layer is formed by exposing the polysilicon stacks to a selected one of at least three ambient reagent gases. The selected gaseous ambient and exposure of the polysilicon stacks being performed in a fabrication tool such as a batch furnace, a single wafer rapid thermal anneal tool, or a plasma chamber.Type: GrantFiled: November 8, 2002Date of Patent: April 6, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Robert B. Ogle, Jr., Arvind Halliyal
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Patent number: 6718439Abstract: An N-way set associative virtual victim cache in which cache accesses are automatically directed only to the data array in the most recently used way. The cache memory comprises: 1) N ways, each of the N ways comprising a data array capable of storing L cache lines and a tag array capable of storing L address tags, each of the L address tags associated with one of the L cache lines; and 2) address decoding circuitry capable of receiving an incoming memory address and accessing a target cache line corresponding to the incoming memory address only in a most recently used one of the N ways.Type: GrantFiled: June 1, 2001Date of Patent: April 6, 2004Assignee: Advanced Micro Devices, Inc.Inventor: Rajeev Jayavant
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Publication number: 20040061227Abstract: A bi-layer BARC/hardmask structure includes a layer of amorphous carbon and two or more distinct and independently formed layers of a PECVD material such as SiON formed on the amorphous carbon layer. By independently forming several layers of PECVD material, at least some pinholes that are present in the lowermost PECVD layer are closed by upper PECVD layers and therefore do not extend through all of the PECVD layers. As a result the upper surface of the uppermost PECVD layer has a lower pinhole density than the lower PECVD layer. This reduces photoresist poisoning by dopant in the amorphous carbon layer, and etching of the amorphous carbon layer by photoresist stripping chemistry.Type: ApplicationFiled: September 27, 2002Publication date: April 1, 2004Applicant: Advanced Micro Devices, Inc.Inventors: Pei-Yuan Gao, Lu You, Richard Huang
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Publication number: 20040061237Abstract: A method for forming a copper interconnect with improved via integrity and elimination of via voiding employs a copper seed layer having an alloy element within the seed layer. The alloy element increases the resistance of the copper seed layer to acidic plating chemistry as the vias are filled and as the pulse-reverse wave form is initiated in the electrochemical plating process. The prevention of void formations at the bottom of the via improves the copper filling, with resulting improved electromigration performance, reduced via resistance and improved product speed.Type: ApplicationFiled: September 26, 2002Publication date: April 1, 2004Applicant: Advanced Micro Devices, Inc.Inventors: Larry Zhao, Paul R. Besser, Connie Wang
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Publication number: 20040061191Abstract: A MOSFET gate or a MOSFET source or drain region comprises silicon germanium or polycrystalline silicon germanium. Silicidation with nickel is performed to form a nickel germanosilicide that preferably comprises the monosilicide phase of nickel silicide. The inclusion of germanium in the silicide provides a wider temperature range within which the monosilicide phase may be formed, while essentially preserving the superior sheet resistance exhibited by nickel monosilicide. As a result, the nickel germanosilicide is capable of withstanding greater temperatures during subsequent processing than nickel monosilicide, yet provides approximately the same sheet resistance and other beneficial properties as nickel monosilicide.Type: ApplicationFiled: December 31, 2002Publication date: April 1, 2004Applicant: Advanced Micro Devices, Inc.Inventors: Eric N. Paton, Qi Xiang, Paul R. Besser, Ming-Ren Lin, Minh V. Ngo, Haihong Wang
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Publication number: 20040060916Abstract: According to one exemplary embodiment, a method for establishing a relationship between Joule heating in a conductor and a current density in the conductor is implemented by performing wafer level measurements. According to this exemplary embodiment, wafer level measurements are performed to arrive at a temperature coefficient of resistance in the conductor. The method also includes determining a thermal resistance of the conductor. The thermal resistance is then utilized to establish a relationship between Joule heating in the conductor and the current density in the conductor. The relationship so obtained is then utilized to determine design rules, mean time to fail, and other information to aid in the design of reliable semiconductor devices. According to another exemplary embodiment, a wafer level measurement system is utilized to establish a relationship between Joule heating in a conductor and a current density in the conductor.Type: ApplicationFiled: September 30, 2002Publication date: April 1, 2004Applicant: Advanced Micro Devices, Inc.Inventors: Huade W. Yao, Amit P. Marathe, Van-Hung Pham
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Publication number: 20040064811Abstract: An improved register allocation technique is provided. An interference graph coloring is attempted multiple times prior to spilling one or more nodes. Each node has a spill cost derived from the time it takes to store and recall the variable's data combined with how often the compiler thinks the variable is needed. Similarly, each coloring failure has a spill cost which is the accumulation of the spill costs of the remaining un-colorable nodes. If any solutions are found, the process is complete. If only failures are found, the cheapest node(s) to spill is evaluated based on the multiple failures. In one embodiment, the cheapest node of the cheapest failure is spilled. In another embodiment, the cheapest node is evaluated across all failures. This process is repeated until a solution is found (all nodes are colored or spilled).Type: ApplicationFiled: September 30, 2002Publication date: April 1, 2004Applicant: Advanced Micro Devices, Inc.Inventor: Morrie Altmejd
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Publication number: 20040061178Abstract: A FinFET device employs strained silicon to enhance carrier mobility. In one method, a FinFET body is patterned from a layer of silicon germanium (SiGe) that overlies a dielectric layer. An epitaxial layer of silicon is then formed on the silicon germanium FinFET body. A strain is induced in the epitaxial silicon as a result of the different dimensionalities of intrinsic silicon and of the silicon germanium crystal lattice that serves as the template on which the epitaxial silicon is grown. Strained silicon has an increased carrier mobility compared to relaxed silicon, and as a result the epitaxial strained silicon provides increased carrier mobility in the FinFET. A higher driving current can therefore be realized in a FinFET employing a strained silicon channel layer.Type: ApplicationFiled: December 31, 2002Publication date: April 1, 2004Applicant: Advanced Micro Devices Inc.Inventors: Ming-Ren Lin, Jung-Suk Goo, Haihong Wang, Qi Xiang
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Publication number: 20040063008Abstract: A method of determining overlay layers utilizing advanced lithographic materials utilizes a post-etch overlay metrology. After etching, a relatively opaque layer is removed so that registration markers such as trench isolation structures can be observed. Lithographic parameters associated with the process can be adjusted in accordance with the observations. In a preferred embodiment, an overlay error is determined and adjustments are made to the reduce the overlay error.Type: ApplicationFiled: September 26, 2002Publication date: April 1, 2004Applicant: Advanced Micro Devices, Inc.Inventors: Cyrus E. Tabery, Christopher F. Lyons, Srikanteswara Dakshina-Murthy
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Patent number: 6713842Abstract: A mask for and method of forming a character on a substrate of a semiconductor device that can be clearly observed even if positioned over complex and random patterns formed on the substrate. The mask includes a transparent medium that includes one or more plurality of regions that each includes a plurality of opaque gratings or lines. The gratings are configured to form a character (or indicia) that contrasts with the remainder of the medium. When light is passed through the mask, the light is refracted off the gratings, thereby producing markedly different colors and/or intensities of light on the substrate. The mask is used during a positive or negative etching process to form a character on a surface of a semiconductor substrate that can be easily viewed by an observer without magnification.Type: GrantFiled: August 17, 2000Date of Patent: March 30, 2004Assignee: Advanced Micro Devices, Inc.Inventor: Terence Manchester
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Patent number: 6713357Abstract: The present invention relates to a method for fabricating MOS transistors with reduced parasitic capacitance. The present invention is based upon recognition that the parasitic capacitance of MOS transistors, such as are utilized in the manufacture of CMOS and IC devices, can be reduced by use of sidewall spacers having an optimized cross-sectional shape, in conjunction with an overlying insulator layer comprised of a low-k dielectric material.Type: GrantFiled: December 20, 2001Date of Patent: March 30, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Hai Hong Wang, Mark W. Michael, Wen-Jie Qi, William G. En, John G. Pellerin
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Patent number: 6715063Abstract: A processor supports a first processing mode in which the address size is greater than 32 bits. The address size may be nominally indicated as 64 bits, although various embodiments of the processor may implement any address size which exceeds 32 bits, up to and including 64 bits, in the first processing mode. The first processing mode may be established by placing an enable indication in a control register into an enabled state and by setting a first operating mode indication and a second operating mode indication in a segment descriptor to predefined states. Other combinations of the first operating mode indication and the second operating mode indication may be used to provide compatibility modes for 32 bit and 16 bit processing compatible with the x86 processor architecture (with the enable indication remaining in the enabled state). To call code operating in the first processing mode from the 32 bit or 16 bit code, a call gate descriptor is defined which occupies two entries in a segment descriptor table.Type: GrantFiled: January 14, 2000Date of Patent: March 30, 2004Assignee: Advanced Micro Devices, Inc.Inventor: Kevin J. McGrath
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Patent number: 6713874Abstract: Degradation of organic-doped silica glass low-k inter-layer dielectrics during fabrication is significantly reduced and resolution of submicron features is improved by the formation of dual nature capping/ARC layers on inter-layer dielectric films. The capping/ARC layer is formed in-situ on the organic-doped silica glass inter-layer dielectric. The in-situ formation of the capping/ARC layer provides a strongly adhered capping/ARC layer, formed with fewer processing steps than conventional capping and ARC layers.Type: GrantFiled: March 27, 2001Date of Patent: March 30, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Dawn M. Hopper, Lu You, Minh Van Ngo