Abstract: A system and method is disclosed for determining a barrier permeability at a via. A test structure is formed having a test barrier between two conductors. A substantially constant current is conducted through the test structure to measure the lifetime of the test structure. A barrier permeability value is assigned to the test barrier of the test structure based on the measured lifetime. The system also includes a test structure having a first conductor, a second conductor forming an interconnect, a no-flux barrier substantially impermeable to mass flux between the first and second conductor, a third conductor, and a test barrier between the second and third conductor, to be assessed for the barrier permeability value. A current source supplies the current through the test structure. A timer measures the lifetime of the test structure, and a processor determines the value of barrier permeability &agr; of the test barrier based on the measured lifetime of the test structure.

Abstract: The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual polysilicon floating gates with an isolation opening between floating gates.

Abstract: Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by treating the exposed surfaces of the silicon nitride sidewall spacers with a nitrogen oxide plasma to create a surface region having reduced free silicon. Embodiments include treating the silicon nitride sidewall spacers with a nitrogen plasma to reduce the refractive index of the surface region to less than about 1.95.

Abstract: Methods and apparatus for inspecting a sample are provided. In one aspect, a method of inspection is provided that includes generating an entangled set of particle beams and directing one of the entangled set of particle beams to a location of a workpiece. One of the entangled set of particle beams interacts with the location of the workpiece. One of the entangled set of particle beams is observed after the interaction with the location of the workpiece to inspect the location of the workpiece.

Abstract: A method of manufacturing a semiconductor device includes forming a first level, forming a first barrier layer over the first level, forming a dielectric layer over the first barrier layer, forming an opening having side surfaces through the dielectric layer, etching the first barrier layer, and filling the opening with metal to form a first metal feature. The process also includes the step of replacing hydroxyl terminated ions on the side surfaces. This step of replacing the hydroxyl terminated ions can occur after the opening is formed or after the first barrier layer is etched. A semiconductor device produced by the method of manufacturing is also disclosed.

Abstract: A switching system includes switches, each having a host processing unit and a switching unit, and a backbone link configured for transferring data packets between the switching units. One of the host processing units is configured as a master unit for generating a data frame having a destination address for a selected one of the switching units of a corresponding selected one of the other host processing units. The master unit outputs the data frame to the corresponding switching unit for transfer to the selected one switching unit via the backbone link. The selected one switching unit, in response to receiving the data frame having the corresponding destination address, forwards the data frame to the corresponding host processing unit for execution of a processing operation specified in the data frame. Hence, the switching system provides inter-processor communications using a preexisting backbone link, eliminating the necessity of a processor bus.

Abstract: A computer system is presented which implements a system and method for conveying packets between a coherent processing subsystem and a non-coherent input/output (I/O) subsystem. The processing subsystem includes a first processing node coupled to a second processing node via a coherent communication link. The first processing node includes a host bridge which translates packets moving between the processing subsystem and the I/O subsystem. The I/O subsystem includes an I/O node coupled to the first processing node via a non-coherent communication link. The I/O node may embody one or more I/O functions (e.g., modem, sound card, etc.). The coherent and non-coherent communication links are physically identical. For example, the coherent and non-coherent communication links may have the same electrical interface and the same signal definition. The host bridge translates non-coherent packets from the I/O node to coherent packets, and transmits the coherent packets to the second processing node.

Abstract: A network switch, configured for performing layer 2 and layer 3 switching in an Ethernet (IEEE 802.3) network without blocking of incoming data packets, includes a plurality of network switch ports each having a filter (i.e., a packet classifier module) configured for evaluating an incoming data packet on an instantaneous basis. The filter performs simultaneous comparisons between the incoming data stream of the data packet and multiple templates configured for identifying respective data protocols, enabling the network switch to perform layer 3 switching for 100 Mbps and gigabit networks without blocking in the network switch. Each template is composed of a plurality of min terms, wherein each min term specifies a prescribed comparison operation within a selected data byte of the incoming data packet. The templates may be programmed by a user and stored in a central min term memory separate from each network switch port.

Abstract: An integrated circuit formed in semiconductor-on-insulator format. The integrated circuit includes a layer of semiconductor material disposed on an insulating layer, where the insulating layer disposed on a substrate. A first and a second MOSFET are provided such that one of a source and a drain of the first MOSFET is disposed adjacent one of a source and a drain of the second MOSFET. An amorphous region is formed in the layer of semiconductor material and extending from an upper surface of the layer of semiconductor material to the isolation layer. The amorphous region is formed between a crystalline portion of the one of the source and the drain of the first MOSFET and a crystalline portion of the one of the source and the drain of the second MOSFET.

Abstract: An apparatus is described in which the locations of a buffer are used to store a plurality of control packets received in a node, wherein the plurality of control packets belong to a plurality of virtual channels. The number of locations assigned to each virtual channel may be dynamically allocated. The number of locations allocated to each virtual channel may be determined by an update circuit. Count values corresponding to the number of locations allocated to each virtual channel may then be stored within a programmable storage, such as a register, for example. The count values may be subsequently copied into a slave register and incremented and decremented as locations become available and notifications corresponding to the available locations are sent, respectively.

Abstract: A process to deposit a silicon dioxide layer on a silicon nitride layer for an ONO stack of a floating gate transistor. Silicon dioxide is deposited on a silicon nitride layer and annealed in a batch furnace or a single wafer rapid thermal anneal tool in a nitrogen oxide (NO) or nitrous oxide (N2O) ambient environment.

Abstract: A scribe seal (22) and a method for manufacturing the scribe seal (22) and a semiconductor component including the scribe seal (22). A semiconductor substrate (24) has a major surface (26) and a crack arrest structure (36) formed on the major surface (26). A dielectric material (30) is formed on a portion of the semiconductor substrate (24) adjacent the crack arrest structure (36). A nitride layer (38) is formed on the crack arrest structure (36) and the dielectric material (30). An oxide layer (40) is formed on the nitride layer (38). An opening (42) is formed in the oxide layer (40) and the nitride layer (38) and lands on and exposes a portion of the dielectric material (30). A crack arrest material such as, for example, copper, is formed in the opening (42). A semiconductor device is formed in the semiconductor substrate (24).

Abstract: An integrated circuit is provided with high-aspect ratio vias in which the upper channel after lining with an adhesion/barrier layer is used as a collimator with a via entrant angle of greater than about 70 degrees during the ionized metal plasma deposition of the seed layer over the adhesion/barrier layer. This results in a seed layer with reduced overhang in the vias enhancing the subsequent filling of the vias by a conductive layer and preventing the formation of voids in the vias.

Abstract: A processor includes an input/output (I/O) register that is mapped into input/output (I/O) address space. The processor also includes a base address register that is loaded with a base address. The base address register may be a model specific register (MSR). The input/output register is accessed with an input/output instruction at an address determined according to the base address and an offset therefrom. The base address register may be accessible to software operating at a high privilege level and not accessible to software operating at a lower privilege level, while the I/O register is accessible to software operating at the lower privilege level. The processor determines when an I/O access is to the processor I/O register and accesses that I/O register without causing an input/output bus cycle that would otherwise occur.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening, a barrier layer lining the channel opening, and a conductor core filling the channel opening. The barrier layer has a more negative heat of formation than the channel dielectric layer whereby the barrier layer is reacts with and forms a barrier to diffusion of the material of the conductor core to the channel dielectric layer. The barrier layer also forms a stable compound with the conductor core to form a coherent barrier layer bonding the channel dielectric to the conductor core.

Abstract: A method and an apparatus are provided for selectively depositing flux on a plurality of flip-chip bumps arranged on a semiconductor chip by jet printing a flux pattern, which is substantially identical to the arrangement pattern of the flip-chip bumps. The flux pattern is determined by measuring the chip configuration and converting the configuration to computer-recognizable data. The converted chip configuration is stored in data storage, and a jet printing head prints the flux pattern based on the computer-recognizable data. A conveyance plate is provided to transport the semiconductor chip to a flux-deposition area below the jet printing head.

Abstract: A method and a system for managing the movement of material lots through a semiconductor fabrication facility. In an example embodiment of the method, the movement of the material lots is tracked and a business rules module is accessed that generates material movement directives as a function of event changes on the line and externally provided directives that change the material lot movement sequence. Material lots are then rearranged in the material handling system as a function of a carrier code and the directive indicating a change. The result is a fabrication process that is more responsive and flexible with respect to internal or external changing conditions.

Abstract: According to one aspect of the disclosure, laser-thermal annealing is used to clear an imaging path through the back side of a semiconductor device after the back side of the chip has been thinned to expose a selected region in the substrate. For many applications, thinning results in the formation of crystal defects that inhibit the ability to obtain images through the back side of the semiconductor device. One example embodiment overcomes this problem by thinning via laser-chemical etching the back side of the semiconductor device under a pressure exceeding a threshold level, and then reducing the pressure to a level below the threshold level and scanning the back side of the semiconductor device using a laser at a reduced power level. IR microscopy is then used to capture an image of a circuit in the circuit side of the semiconductor device through the back side of the semiconductor device. One particular example application is directed to a flip-chip semiconductor device.

Abstract: An optical tool includes a tool body that is transparent to light. Pluralities of parallel opaque lines on the body form a first outline in the shape of the square, and a second outline in the shape of a square which is centrally located relative to and within the first-mentioned square. Each pair of adjacent parallel lines has therebetween a first region that allows transmission of light therethrough without changing phase thereof, and a second region alongside the first region that allows transmission of light therethrough while shifting the phase thereof by 90°. The phase shifting and non-phase shifting regions are positioned so that the images of the outlines provided by a lens on an object shit in position a substantial amount as the distance between the lens and the object is changed.

Abstract: For fabricating a shallow trench isolation structure, a notched masking structure is formed over an active area of a semiconductor substrate. A shallow trench opening is formed at a side of the active area with a top corner of the shallow trench opening being exposed and facing a notched surface of the notched masking structure. Liner oxide is formed in a thermal oxidation process at the top corner of the shallow trench opening to round the top corner of the shallow trench opening. The liner oxide may also be formed on walls including the bottom corner of the shallow trench opening during the thermal oxidation process. The shallow trench opening is then filled with a trench dielectric material to form the shallow trench isolation structure.