Abstract: A method of fabricating an integrated circuit can include forming a laminated conductive line. The laminated conductive line can be formed in a dielectric trench. The laminated conductive line can include alternating barrier layers and copper layers. An integrated circuit includes at least one interconnect layer, the interconnect layer including a number of conductive lines. Each of the conductive lines includes a first thin barrier layer, a first thin copper layer, a second thin barrier layer and a second thin copper layer. The layered or laminated structure can reduce unconstrained void formation.

Abstract: A peripheral interface circuit for an I/O node of a computer system. A peripheral interface circuit for an input/output node of a computer system includes a first buffer circuit, a second buffer circuit and a bus interface circuit. The first buffer circuit receives packet commands and may include a first plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels. The second buffer circuit is coupled to receive packet commands from the bus interface circuit and may include a second plurality of buffers each corresponding to a respective virtual channel of the plurality of virtual channels. The bus interface circuit may be configured to translate selected packet commands stored in the first buffer circuit into commands suitable for transmission on a peripheral bus.

Abstract: A system-on-a-chip with a variable bandwidth bus. The integrated circuit includes at least one bus, a clock, a plurality of modules coupled to the bus and operable to transfer and receive data on the bus, and a bus controller coupled to the bus that controls data transfers on the bus. The modules are operable to generate requests to the bus controller to perform transfers on the bus. Each request comprises an identifier which identifies one or more receiving modules, a transfer size value which specifies the amount of data to be transferred, and a timing value providing a time frame within which the requested data transfer should occur.

Abstract: Low-k ILDs are protected from degradation during damascene processing by depositing a thin, conformal silicon carbide liner with a silicon-rich surface before barrier metal layer deposition. Embodiments include forming a dual damascene opening in porous low-k dielectric layers, depositing a thin silicon carbide liner with a silicon-rich surface lining the opening, depositing a barrier metal layer, such as a Ta/TaN composite, and filling the opening with Cu.

Abstract: A network switch having switch ports for communication of data packets with respective computer network nodes according to CSMA/CD protocol that resets a retry counter for counting data packet transmission attempts within any one of the respective switch ports if backpressure is asserted by that port. A retry limit value for the retry counter is selectively modified according to programmed information to ensure that the total number of retrys does not exceed a maximum total number of allowable retrys. Resetting the retry counter within a port after assertion of backpressure affords the port a greater probability of transmitting earlier under the CSMA/CD protocol, thus more quickly relieving congestion which may occur in the network switch. Selective modification of the retry limit value according to programmed information adds flexibility to vary the maximum total number of allowable retrys based upon current network switch conditions or the priority of a particular data packet.

Abstract: In a method of fabricating a semiconductor device, a gate oxide layer is provided on a silicon substrate. A first polysilicon layer is provided on the gate oxide layer, a dielectric layer is provided on the first polysilicon layer, and a second polysilicon layer is provided on the dielectric layer. Upon appropriate masking, an etch step is undertaken, etching the second polysilicon layer, dielectric layer, first polysilicon layer, and gate oxide layer to remove portions thereof to expose the silicon substrate and to form a stacked gate structure on the silicon substrate. A rapid thermal anneal is undertaken for a short period of time, i.e., for example 10-20 seconds, to grow a thin oxide layer on the stacked gate structure. Then, another oxide layer is deposited over the oxide layer which was formed by rapid thermal anneal.

Abstract: A semiconductor device structure comprises a corner structure enclosed by a delineation region, wherein the shape of the corner structure does not exhibit any symmetry with respect to point symmetry and axial symmetry, such that the corner structure is unambiguously recognizable by an automated alignment system. Furthermore, the inner region of the corner structure may be filled with a pattern indicating the type of material layer in which the corner structure is formed. The corner structure exhibits a strong contrast even if the wafer is subjected to a CMP treatment.

Abstract: Multiple network switch modules have memory interfaces configured for transferring packet data to respective buffer memories. The memory interfaces are also configured for transfer among each other data units of data frames received from different network switch modules. The memory interfaces transfer the data units according to a prescribed sequence, optimizing memory bandwidth by concurrently executing a prescribed number of successive memory writes or memory reads. An alternative embodiment includes a distributed memory interface in between the network switch modules and a shared memory system, where the width of the data bus of the shared width memory system equals the total number of bits on the data buses of the switch modules.

Abstract: Semiconductor devices comprising interconnects with improved adhesion of barrier layers to dielectric layers are formed by laser thermal annealing, in N2 and H2, exposed surfaces of a dielectric layer defining an opening, and then depositing Ta to form a composite layer lining the opening. Embodiments include forming a dual damascene opening in an interlayer dielectric comprising F-containing dielectric material, such as F-silicon oxide derived from F-TEOS, impinging a pulsed laser light beam on exposed surfaces of the F-silicon oxide defining the opening in a flow of N2 and H2, and then depositing Ta to form a composite barrier layer comprising graded tantalum nitride and &agr;-Ta lining the opening. Laser thermal annealing in N2 and H2 depletes the exposed silicon oxide surfaces of F while enriching the surfaces with N2. Deposited Ta reacts with the N2 in the N2-enriched surface region to form a composite barrier layer comprising a graded layer of tantalum nitride and a layer of &agr;-Ta thereon.

Abstract: For aggressively scaled field effect transistors, nitrogen is incorporated into a base oxide layer, wherein, at an initial phase of a plasma nitridation process, the nitrogen ion density is maintained at a value so that incorporation of nitrogen into the channel region is minimized. Subsequently, when the thickness of the base oxide layer has increased, due to residual oxygen in the plasma ambient, the nitrogen ion density is increased, thereby increasing the nitridation rate. Preferably, the nitrogen ion density is controlled by varying the pressure of the plasma ambient. Moreover, a system is disclosed that allows control of the nitridation rate in response to an oxide layer thickness.

Abstract: One aspect of the present invention relates to a system and method of monitoring for defects on a wafer before and after forming a photoresist layer on the wafer. The system includes a device fabrication system comprising one or more wafer processing system components for producing a device; a defect metrology system integrated within and on track with the fabrication system operative to inspect the wafer for defects before it proceeds to photoresist processing; and a wafer cleaning system for reducing an amount of defects detected on the front and/or back side of the wafer. If the amount of defects have been sufficiently reduced, the front side of the wafer may be coated with a photoresist. Subsequently, the back side of the wafer may be inspected and cleaned while protecting the front side from damage. Cleaning of the wafer may be performed with a thermal shock treatment, for example.

Abstract: A method is provided for manufacturing a MirrorBit® Flash memory with high conductivity bitlines and shallow trench isolation integration. A hard mask is formed over a substrate and used to form a core trench and a shallow trench isolation (STI) trench. The trenches are filled with an insulating material in an STI fill process. A core mask is formed over the STI trenches and exposing the core trenches. The insulating material is removed from the core trenches and the core and hard mask are removed. A doped bitline material is deposited on the surface of the semiconductor, which fills the core trench. The surface of the semiconductor is planarized, inlaying insulating material and doped bitline material in the trenches. A thermal anneal causes the dopant diffusion from the doped bitline material into the substrate to form the high conductivity bitlines.

Abstract: Various embodiments of a planarization device and methods of using the same are provided. In one aspect, a device for planarizing a surface of a semiconductor workpiece is provided that includes a table for holding a quantity of an electrically conducting solution thereon. A member is included for holding the semiconductor workpiece such that the surface is in contact with the solution and operates as a working electrode. The member has a first conductor for establishing electrical connection with the semiconductor workpiece. A counter electrode is provided for making electrical connection with the solution and a reference electrode is provided for making electrical connection with the solution with a known electrode potential. A power source is operable to control the electric potential between the working electrode and the counter electrode. Slurry consumption may be dramatically reduced and static etch rate due to aborts may be virtually eliminated.

Abstract: A method and apparatus for providing fault detection in an Advanced Process Control (APC) framework. A first interface receives operational state data of a processing tool related to the manufacture of a processing piece. The state data is sent from the first interface to a fault detection unit. A fault detection unit determines if a fault condition exists with the processing tool based upon the state data. A predetermined action is performed on the processing tool in response to the presence of a fault condition. In accordance with one embodiment, the predetermined action is to shutdown the processing tool so as to prevent further production of faulty wafers.

Abstract: A method of forming source/drain regions in a semiconductor device is provided. In one illustrative embodiment, the method comprises forming a gate electrode above a semiconducting substrate, forming source/drain regions in the substrate adjacent the gate electrode by performing at least the following steps: performing two ion implantation processes to form source/drain extensions for the device and performing a third ion implantation process to further form source/drain regions for the device. Various N-type and P-type dopant atoms such as arsenic, phosphorous, boron and boron difluoride may be used with the present invention.

Abstract: An arbitration mechanism for an input/output node of a computer system. An arbitration mechanism includes a buffer circuit for storing received control commands corresponding to a posted virtual channel and a second virtual channel. Each of the control commands includes an identifier value indicative of the source of the control command. A tag circuit that may generate a tag value for each of the control commands prior to the control commands being stored. The tag value may be indicative of an order of receipt of each of the control commands relative to other control commands and may be dependent upon the identifier value. In addition, an arbitration circuit may arbitrate between control commands stored within the buffer circuit dependent upon the tag value of each of the control commands. The arbitration circuit may select, independently of the tag values, a given control command and having a flag bit set.

Abstract: A method of manufacturing an integrated circuit includes a semiconductor substrate having bitlines under a charge-trapping material over a core region and a gate insulator material over a periphery region. A wordline-gate material, a hard mask, and a first photoresist are deposited and patterned over the core region while covering the periphery region. After removing the first photoresist, wordlines are formed from the wordline-gate material in the core region. An anti-reflective coating and a second photoresist are deposited and patterned over the periphery region and covering the core region. The anti-reflective coating is removable without damaging the charge-trapping material. After removing the second photoresist and the anti-reflective coating, gates are formed from the wordline-gate material in the periphery region and the integrated circuit completed.

Abstract: A computer system is presented which implements a system and method for tracking the progress of posted write transactions. In one embodiment, the computer system includes a processing subsystem and an input/output (I/O) subsystem. The processing subsystem includes multiple processing nodes interconnected via coherent communication links. Each processing node may include a processor preferably executing software instructions. The I/O subsystem includes one or more I/O nodes. Each I/O node may embody one or more I/O functions (e.g., modem, sound card, etc.). The multiple processing nodes may include a first processing node and a second processing node, wherein the first processing node includes a host bridge, and wherein a memory is coupled to the second processing node. An I/O node may generate a non-coherent write transaction to store data within the second processing node's memory, wherein the non-coherent write transaction is a posted write transaction.

Abstract: A semiconductor structure that includes an electrically conductive probe that extends from the back side of an integrated circuit to a selected region within the substrate. The structure includes a substrate having first and second surfaces. An active region is disposed in the substrate, and an electrically conductive probe extends from the first surface of the substrate to the active region. Probes can also be constructed to connect one to another and with well regions within the substrate.

Abstract: A clamping circuit and method for use in a computer system are provided. In the computer system, a voltage regulator supplies a voltage rail to various components in the system. This voltage rail may be susceptible to voltage spikes or other over-voltage conditions, such as when the voltage rail provides the input voltage to a switching regulator. The clamping circuit comprises a detecting stage and a clamping stage. The detecting stage detects when the voltage rail increases beyond a first voltage level. If this increase is detected, the detecting stage activates the clamping stage, which begins reducing the voltage rail. Once the voltage rail decreases beneath the first voltage level, the detecting stage stops activating the clamping stage. In this way, the clamping circuit protects the computer system from voltage spikes on the voltage rail.