Abstract: To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.

Abstract: A method is presented to increase, by means of dummy via or contact structures, the open areas to 5% or more of the total wafer area in a semiconductor manufacturing process, e.g., contact/via etch processes for interconnect layers. An open area of 5% or more allows robust endpoint detection using optical emission from the plasma, or electrical signals from the RF system. An end-pointed via/contact etch process overcomes the problems encountered due to the effects of aspect-ratio dependent etching, etch rate differences between tools, etch rate fluctuations over time, and deviations of mean incoming film thickness. With end-pointed etching, only the sources of non-uniformity over the wafer have to be considered during etch, which reduces the amount of over-etch built into a conventional via/contact etch process. The dummy structures may be redundant (functional) structures or “true” dummy (non-functional) structures. The dummy structures have the same size as functional structures.

Abstract: A flash memory array having multiple dual bit memory cells divided into section attached to a wordline and a pair of reference cells logically associated with each section. A method of reprogramming a section or sections of words that are required to be changed includes inputting allowed changes to the flash memory array, reading word or words to be changed in each section, programming bits in word or words to be changed in each section, refreshing previously programmed bits in the word or words that are changed, refreshing previously programmed bits in the word or words changed in each section, refreshing previously programmed bits in the remaining word or words in each section and refreshing previously programmed in each pair of reference cells in the section in which changes have been made.

Abstract: There is disclosed a reduced noise line driver for driving a signal line in an integrated circuit. The reduced-noise line driver comprises: 1) an N-type transistor having a source coupled to ground and a drain coupled to the signal line; 2) a P-type transistor having a source coupled to a power supply rail and a drain coupled to the signal line; 3) a first controller having an input for receiving an incoming signal and an output coupled to a gate of the N-type transistor; and 4) a second controller having an input for receiving the incoming signal and an output coupled to a gate of the P-type transistor, wherein the first controller and the second controller selectively switch the N-type transistor and the P-type transistor ON and OFF such that the N-type transistor and the P-type transistor are never ON simultaneously.

Abstract: A method includes processing a workpiece in accordance with a first operating recipe. The workpiece is processed in accordance with a second operating recipe subsequent to processing the workpiece in accordance with the first operating recipe. A characteristic of the workpiece is measured after processing in accordance with the second operating recipe. An operating recipe parameter is determined for the first operating recipe based on the measured characteristic. A processing line includes first and second process tools, a metrology tool, and a controller. The first process tool is configured to process a workpiece in accordance with a first operating recipe. The second process tool is configured to process the workpiece in accordance with a second operating recipe subsequent to the processing of the workpiece in accordance with the first operating recipe by the first process tool. The metrology tool is configured to measure a characteristic of the workpiece after processing in the second process tool.

Abstract: A networking interface device for coupling a system host having one of a plurality configurations to a network medium. The networking interface device has a peripheral component interconnect (PCI) interface for coupling the interface device to a system host configured with a PCI based system bus interface; a medium independent interface (MII) for coupling the interface device to a system host configured with a media access controller (MAC) based system bus interface; and a buffer management device (BMU) having an active state for bursting data packet traffic via the PCI interface when the interface device is coupled to a PCI based system bus interface and a passive state for continuously passing data packet traffic via the MII when the interface device is coupled to a MAC based system bus interface.

Abstract: The operability of light-based semiconductor die analysis is enhanced using a method and arrangement that can detect light leakage between a light source and a die. In one example embodiment of the present invention, a light source is directed to a semiconductor analysis arrangement using, for example, a fiber optic cable. The analysis arrangement is adapted to use light from the light source for analyzing the die. A light detection arrangement detects a condition of light leakage from the system and generates a signal representing the condition of light leakage. The generated signal can then be used to control the semiconductor analysis arrangement, such as by deactivating the light source in response to a detected leak, or by allowing the light source to function in response to not detecting a leak.

Abstract: In a memory array, a plurality of sectors are included. Each sector includes a plurality of parallel bit lines which lie in a plane. Sector connecting lines connect the sectors. These sector connecting lines are parallel to each other and to the bit lines. The sector connecting lines include a first set of sector connecting lines which lie in a plane parallel to and adjacent and spaced from the plane of the bit lines, and a second set of sector connecting lines which lie in a plane parallel to and adjacent and spaced from the plane of the first set of sector connecting lines. When viewed across the sector, consecutive sector connecting lines lie in the two different planes thereof in alternating manner, i.e., the sector connecting lines are in a staggered relation.

Abstract: A method for reducing the time for a partially depleted/silicon-on-insulator (PD/SOI) based circuit to reach a dynamic steady state pre-conditions the PD/SOI-based circuit by initially charging the circuit at a voltage greater than the normal operating voltage. The circuit is then charged at the normal operating voltage after a predetermined amount of time. By pre-conditioning the circuit in this manner, the amount of time required for the PD/SOI transistors of the circuit to reach their dynamic steady state (DSS) condition is shortened.

Abstract: Tracking the movement of individual wafers in a semiconductor processing system is improved by using an apparatus to axially rotate a wafer and using both the rotation angle and the wafer's location in the processing system as tracking coordinates. In an example embodiment, the apparatus imparts angles of rotation on the wafers in different stages of wafer processing. The rotation angles of each wafer are collected as data along with the wafer's location in the process. The combined wafer location and angle of rotation data are used to map the path the wafer has traveled from the onset of processing. An important advantage to this apparatus is the increased control and improved yields that the apparatus brings to wafer processing.

Abstract: Various circuit structures incorporating masks and anti-reflective coatings and methods of fabricating the same are provided. In one aspect, a circuit structure is provided that includes a substrate and a first photosensitive film on the substrate. The first photosensitive film is photosensitive to a first electromagnetic spectrum and anti-reflective of a second electromagnetic spectrum that differs from the first electromagnetic spectrum. A second photosensitive film is on the first photosensitive film. The second photosensitive film is photosensitive to the second electromagnetic spectrum whereby exposure by the second electromagnetic spectrum will activate the second photosensitive film but not the first photosensitive film and exposure by the first electromagnetic spectrum will activate unmasked portions of the first photosensitive film. The first photosensitive film doubles as an anti-reflective coating that may be patterned anisotropically using lithographic techniques.

Abstract: A manufacturing method is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. By using a polishing solution having a high selectivity from the conductor core to the barrier layer in conjunction with a grooved polyurethane polish pad, a very thin barrier layer may be used without the conductor core and dielectric layer being subject to erosion and the conductor core being subject to dishing.

Abstract: Methods and apparatus are provided for measuring contaminant mobile ions in a dielectric portion of a semiconductor. The apparatus is comprised of a heat source configured to elevate a temperature of the dielectric portion of the semiconductor and mobilize the contaminant mobile ions. The apparatus is also comprised of a fluid source configured to expose the dielectric portion of the semiconductor to a mobilizing fluid having contaminant ion releasing atoms that assists in mobilizing the contaminant mobile ions. The apparatus further comprises a mobile ion measurement unit configured to perform measurements of the contaminant mobile ions in the dielectric portion of the semiconductor.

Abstract: A network switch, configured for performing layer 2 and layer 3 switching in an Ethernet (IEEE 802.3) network without blocking of incoming data packets, includes a network switch port having a filter (i.e., a packet classifier module) configured for evaluating an incoming data packet on an instantaneous basis. The filter performs simultaneous comparisons between the incoming data stream of the data packet and multiple templates configured for identifying respective data protocols. Each template is composed of a plurality of min terms, wherein each min term specifies a prescribed comparison operation within a selected data byte of the incoming data packet. The templates may be programmed by a user and stored in an internal min term memory. Moreover, the multiple simultaneous comparisons enable the network switch to perform layer 3 switching for 100 Mbps and gigabit networks without blocking in the network switch.

Abstract: A polishing head and an apparatus for the chemical mechanical polishing (CMP) of a substrate are provided in which a conditioning surface is integrated in or directly coupled to the polishing head so that a simplified structure of the CMP apparatus can be obtained. Furthermore, establishing quite similar pad conditions may be achieved. Preferably, the conditioning surface is integrated into the retaining element of sophisticated CMP apparatuses, thereby allowing the application of an adjustable pressure to the conditioning surface.

Abstract: In forming an opening or space in a substrate, a layer of photoresist is provided on the substrate, and the photoresist is patterned to provide photoresist bodies having respective adjacent sidewalls. A polymer layer is provided on the resulting structure through a low temperature conformal CVD process. The polymer layer is anisotropically etched to form spacers on the respective adjacent sidewalls of the photoresist bodies. The substrate is then etched using the spacers as a mask.

Abstract: A method for prioritizing production flow includes processing a plurality of manufactured items in a process flow; measuring characteristics of a plurality of manufactured items in the process flow; estimating performance grades for the plurality of manufactured items based on the measured characteristics; grouping the manufactured items with like estimated performance grades; assigning priorities to groups of manufactured items with like estimated performance grades; and directing the plurality of manufactured items through the process flow based on the assigned priorities. A manufacturing system includes a plurality of processing tools adapted to process a plurality of manufactured items in a process flow, a metrology tool, and a process control server. The metrology tool is adapted to measure characteristics of a plurality of manufactured items in the process flow.

Abstract: A network switch configured for switching data packets across multiple ports uses numerous digital registers to process signals in support of the switch's functionalities. The design parameters associated with these registers are readily modifiable by storing these parameters in a central storage system. These design parameters are automatically read into the source code of a hardware description language, whereby the values and definitions of the registers are modified without altering the source code. Accordingly, any source code requiring updated bit definition and default values is automatically initialized without concern over design mismatch.

Abstract: A network switch, configured for performing layer 2 and layer 3 switching in an Ethernet (IEEE 802.3) network without blocking of incoming data packets, includes a switching module having a shared address table storing address entries for both layer 2 and layer 3 address search operations for layer 2 and layer 3 processing. The shared address table is configured for storing in each address entry two key entries, and two pointer fields, enabling each address entry of the shared address table to logically belong to two separate and independent tables for search purposes.

Abstract: A method and an apparatus for performing modeling of batch dynamics in processing of semiconductor wafers. The method includes performing the process on the first semiconductor wafer in a lot, the process being controlled by a tool model, and acquiring integrated metrology data related to the process of the first semiconductor wafer using an integrated metrology tool. The method further includes performing a lot dynamic modeling process based upon an analysis of the integrated metrology data, the lot dynamic modeling process comprising adjusting the tool model based upon analysis of the integrated metrology data, and performing the process on a second semiconductor wafer in the lot based upon the adjusted tool model.