Patents Assigned to Advanced Micro Devices, Inc.
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Patent number: 6625683Abstract: A bus bridge mechanism is provided with an automatic delayed transaction enable mode. When the automatic delayed transaction enable mode is activated, a bus master making a read request is immediately signaled to retry the transaction, and the read request is treated by the bus bridge as a delayed read request to be completed asynchronously. The delayed read request, when completed, supplies data to the bus master on the next retry of the read request by the bus master following the completion of the delayed read request.Type: GrantFiled: August 23, 1999Date of Patent: September 23, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Asif Q. Khan, James O. Mergard
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Patent number: 6624642Abstract: Disclosed is a wafer containing a semiconductor substrate, at least one metal layer formed over the semiconductor substrate, and at least one electrical sensor embedded at least one of on and in the wafer to facilitate real time monitoring of the metal layer as it progresses through a subtractive metallization process. The system contains a wafer comprising at least one metal layer formed on a semiconductor substrate, at least one electrical sensor in contact with the wafer and operable to detect and transmit electrical activity associated with the wafer, and an electrical measurement station operable to process electrical activity detected and received from the electrical sensor for monitoring a subtractive metallization process in real-time.Type: GrantFiled: December 10, 2001Date of Patent: September 23, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Christopher F. Lyons, Ramkumar Subramanian, Steven C. Avanzino
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Patent number: 6622547Abstract: A system and method for evaluating optical proximity corrected (OPC) designs is provided. The system includes an AFM measurement system for performing measurements relating to a segment of a feature pattern corresponding to a predetermined OPC mask feature. The measurement system is configured to determine a first image for the segment of the printed feature based upon the measurements. The measurement system compares the first image with another image corresponding to different OPC design to evaluate performance characteristics of the respective OPC designs.Type: GrantFiled: July 17, 2002Date of Patent: September 23, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Khoi Phan, Ramkumar Subramanian, Bhanwar Singh
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Patent number: 6625726Abstract: A method and apparatus for fault handling in computer systems. In one embodiment, a first register is used to store an address which points to the top of a stack. The address stored in the first register may be updated during the execution of an instruction. A second register may be used to store an address previously first register. The contents of the second register may be kept unchanged until the retirement of the instruction that is currently executing. If a fault occurs during execution of the instruction, a microcode fault handler may perform routines that may clear the fault or those conditions which led to the fault. The microcode fault handler may also copy the contents of the second register back into the first register. Execution of the instruction may be restarted from the operation just prior to when the fault occurred. The program from which the instruction originated may then continue to run.Type: GrantFiled: June 2, 2000Date of Patent: September 23, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Michael T. Clark, Scott A. White
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Patent number: 6624035Abstract: The present invention is directed to a method of forming halo implants in a semiconductor device. In one illustrative embodiment, the method comprises forming a gate electrode above a surface of a semiconducting substrate, and forming a hard mask layer above the gate electrode and the substrate. The method further comprises patterning the hard mask layer to define an opening in the hard mask layer, and performing an angled implantation process through the opening in the hard mask to introduce dopant atoms into the substrate under at least a portion of the gate electrode.Type: GrantFiled: March 13, 2000Date of Patent: September 23, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Scott D. Luning, David Donggang Wu, Massud Aminpur
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Patent number: 6621761Abstract: A burst mode architecture to provide burst mode access to a plurality of data words in a flash memory is described. The burst mode architecture includes a first circuit, a control circuit coupled to the first circuit, and a data buffer selectively coupled to the first circuit by the control circuit. The first circuit accesses a plurality of data words, beginning with an initial access of a first data word and a second data word. The control circuit generates a timing signal having pulses and a second signal. The second signal is generated upon completion of the initial access of the first data word and the second data word. The first circuit follows the initial access with subsequent accesses of the plurality of data words responsively to the second signal and the timing signal.Type: GrantFiled: April 9, 2001Date of Patent: September 16, 2003Assignees: Advanced Micro Devices, Inc., Fujitsu LimitedInventors: Takao Akaogi, Lee Cleveland, Kendra Nguyen
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Patent number: 6621043Abstract: A method of calibrating a laser utilized in a laser element cutting system utilizing a mechanical gauge having pairs of metal pads formed in rows and columns on a substrate material. The height of the metal pads varies in each row with each column having the same height. The depth of the substrate material under the metal pads varies. The mechanical gauge is subjected to a laser cut process and the mechanical gauge is illuminated by a light source. The light shining through positions of metal pads indicates that the metal pad and the underlying substrate material have been cut. The depth of cut is determined from the thickness of the metal layer and the thickness of the substrate material that have been cut.Type: GrantFiled: November 9, 2001Date of Patent: September 16, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Don Lambert, Valerie Vivares, Ajit M. Dubey
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Patent number: 6622061Abstract: The present invention provides for a method and apparatus for correction of overlay control errors. Semiconductor devices are processed based upon control input parameters. The processed semiconductor devices are examined in a review station. The control input parameters are modified in response to the examination of the processed semiconductor devices. New control input parameters are implemented for a subsequent run of the semiconductor device processing step based upon the modification of the control input parameters.Type: GrantFiled: May 31, 2002Date of Patent: September 16, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Anthony J. Toprac, Christopher A. Bode, Richard D. Edwards
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Patent number: 6620717Abstract: A method of manufacturing for a Flash memory includes depositing a charge-trapping material over a semiconductor substrate and implanting first and second bitlines. A wordline material is deposited over the charge-trapping dielectric material and a hard mask material deposited. A disposable anti-reflective coating (ARC) material and a photoresist material are deposited followed by processing to form a patterned photoresist material and a patterned ARC material. The hard mask material is processed to form a patterned hard mask material. The patterned photoresist is removed and then the patterned ARC without damaging the patterned hard mask material or the wordline material. The wordline material is processed using the patterned hard mask material to form a wordline and the patterned hard mask material is removed without damaging the wordline or the charge-trapping dielectric material.Type: GrantFiled: March 14, 2002Date of Patent: September 16, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Tazrien Kamal, Scott A. Bell, Kouros Ghandehari, Mark T. Ramsbey, Jeffrey A. Shields, Jean Y. Yang
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Patent number: 6620671Abstract: A method of manufacturing an integrated circuit on a substrate provides a gate structure including single crystalline material. The method can provide a first amorphous or polycrystalline semiconductor layer above a top surface of the substrate and patterning the first amorphous semiconductor layer to form a first gate conductor. The process can also include utilizing solid phase epitaxy to form a single crystal layer above the first gate conductor and patterning the single crystal layer to form a second gate conductor including the single crystal layer.Type: GrantFiled: May 1, 2001Date of Patent: September 16, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Haihong Wang, Joong Jeon
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Patent number: 6622201Abstract: A sequential access memory structure includes an output bus and a plurality of sequential access memories, each of which is connected to the output bus. Each memory includes a memory array having a plurality of sequentially readable memory elements, a carry output for producing a carry signal when reading of the array has been substantially completed, and a carry input for causing reading of the array in response to a carry signal. The carry output of each memory is connected to a carry input of one other downstream memory respectively in a chain arrangement, and the carry signals cause the arrays to be read sequentially onto the output bus. Each memory further comprises a read-write storage connected between the array and the output bus, the storage including a plurality of sections. Data from the array is loaded into one section of the storage while data is being read from another section of the storage onto the output bus. The sections of memory elements in the array comprise half-pages.Type: GrantFiled: March 14, 2000Date of Patent: September 16, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Michael VanBuskirk, Pau-Ling Chen
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Patent number: 6620718Abstract: The present invention is directed to a method of forming metal silicide regions on a gate electrode (23) and on the source/drain regions (25) of a semiconductor device (100). In one illustrative embodiment, the method comprises forming a gate stack (17) above a semiconducting substrate (20), the gate stack (17) being comprised of a gate electrode (23) and a protective layer (24), forming a plurality of source/drain regions (25) in the substrate (20), and forming a first metal silicide region (28) above each of the source/drain regions (25). The method further comprises removing the protective layer (24) from above the gate electrode (23) and forming a second metal silicide region (31) above the gate electrode (23).Type: GrantFiled: April 25, 2000Date of Patent: September 16, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Karsten Wieczorek, Michael Raab, Rolf Stephan
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Patent number: 6622235Abstract: A scheduler issues memory operations without regard to whether or not resources are available to handle each possible execution outcome of that memory operation. The scheduler also retains the memory operation after issuance. If a condition occurs which prevents correct execution of the memory operation, the memory operation is retried. The scheduler subsequently reschedules and reissues the memory operation in response to the retry. Additionally, the scheduler may receive a retry type indicating the reason for retry. Certain retry types may indicate a delayed reissuance of the memory operation until the occurrence of a subsequent event. In response to such retry types, the scheduler monitors for the subsequent event and delays reissuance until the event is detected. The scheduler may include a physical address buffer to detect a load memory operation which incorrectly issued prior to an older store memory operation upon which it is dependent for the memory operation.Type: GrantFiled: January 3, 2000Date of Patent: September 16, 2003Assignee: Advanced Micro Devices, Inc.Inventors: James B. Keller, Ramsey W. Haddad, Stephan G. Meier
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Patent number: 6622111Abstract: The movement of individual wafers in a semiconductor facility is tracked via a set of coordinates that include rotational points of reference on the wafer that coincide with the wafer's location in the processing line. In an example embodiment, the method includes imparting angles of rotation on the wafers in different stages of the processing system. The different angles of rotation on each wafer are collected as data along with the wafer location in the processing system and the tool/equipment identification code. The combined angle of rotation and wafer location data is used to map the path the wafer has traveled from the onset of processing. An important advantage of the invention is the increased control and traceability that the invention brings to wafer processing.Type: GrantFiled: March 8, 2000Date of Patent: September 16, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Michael R. Conboy, Elfido Coss, Jr., Sam H. Allen, Jr.
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Patent number: 6621290Abstract: A test structure and method for testing a semiconductor material is provided with a semiconductor wafer having an electrical ground and a source of electrical potential. A conductor layer is placed over the semiconductor wafer and a semiconductor material is placed over the conductor layer. A dielectric layer is placed over the semiconductor material. Conductive top and bottom layers are placed over the dielectric layer and the bottom of the semiconductor wafer. The conductive top layer is connected to the electrical ground. The conductive bottom layer is connected to the source of electrical potential. The current flow is measured from the conductive bottom layer to the conductive top layer.Type: GrantFiled: July 13, 2001Date of Patent: September 16, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Amit P. Marathe, Pin-Chin Connie Wang
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Patent number: 6620705Abstract: A method of forming a dielectric structure for a flash memory cell includes forming a first layer of silicon dioxide, forming a layer of silicon nitride on the first layer of silicon dioxide, and pretreating the silicon nitride layer. Pretreatment of the silicon nitride layer includes nitridation. The method further includes depositing a second layer of silicon dioxide on the pretreated silicon nitride layer. Nitridation of the silicon nitride can occur in a batch process or in a single wafer tool, such as a single wafer rapid thermal anneal (RTA) tool. The nitriding pretreatment of the nitride layer improves the integrity of the ONO structure and enables the second layer of silicon dioxide to be deposited rather than thermally grown. Because the nitride layer undergoes less change after deposition of the second layer of silicon dioxide, the present method improves the overall reliability of the ONO structure.Type: GrantFiled: December 5, 2001Date of Patent: September 16, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Robert B. Ogle, Arvind Halliyal
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Patent number: 6622237Abstract: A processor employs a store to load forward (STLF) predictor which may indicate, for dispatching loads, a dependency on a store. The dependency is indicated for a store which, during a previous execution, interfered with the execution of the load. Since a dependency is indicated on the store, the load is prevented from scheduling and/or executing prior to the store. The STLF predictor is trained with information for a particular load and store in response to executing the load and store and detecting the interference. Additionally, the STLF predictor may be untrained (e.g. information for a particular load and store may be deleted) if a load is indicated by the STLF predictor as dependent upon a particular store and the dependency does not actually occur. In one implementation, the STLF predictor records at least a portion of the PC of a store which interferes with the load in a first table indexed by the load PC.Type: GrantFiled: January 3, 2000Date of Patent: September 16, 2003Assignee: Advanced Micro Devices, Inc.Inventors: James B. Keller, Thomas S. Green, Wei-Han Lien, Ramsey W. Haddad, Keith R. Schakel
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Patent number: 6621412Abstract: Several different embodiments of a troubleshooting method are described. In one embodiment, an alarm data image is provided (e.g., to a user). The alarm data image may be displayed upon on a display screen visible by the user. The alarm data image includes an image indicative of a problem (e.g., an abnormal condition or faulty state of a processing or metrology tool). Information indicative of a class in which the problem resides is used to access a corresponding portion of a troubleshooting guide (TSG). The corresponding portion of the TSG includes one or more symptom images, wherein each symptom image includes an image indicative of a symptom of the class in which the problem resides. Each symptom image has a corresponding corrective action. A selected one of the symptom images is selected (e.g., by the user). Where the selecting is performed by the user, the user may select one of the symptom images the user believes most closely resembles the alarm data image.Type: GrantFiled: February 14, 2001Date of Patent: September 16, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Richard J. Markle, Elizabeth Weaver
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Patent number: 6622274Abstract: There is provided an improve BIST frontend state machine and a method for micro-architectural implementation of the same which is achieved with a minimal amount of test logic circuitry. The state frontend machine includes a state controller responsive to clock signals, control signals, and output register signals for generating output state signals based upon a fixed number of states utilizing death logic so as to sequence through one of a plurality of sets of tests until completed or failed. A substantial savings of approximately 40% in the I.C. chip area was realized in comparison to the implementation by a conventional state machine.Type: GrantFiled: September 5, 2000Date of Patent: September 16, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Weng F. Lee, Colin S. Bill, Feng Pan, Edward V. Bautista
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Patent number: 6621281Abstract: Analysis of a semiconductor die having silicon-on-insulator (SOI) structure is enhanced by accessing the circuitry within die from the back side without breaching the thin insulator layer of the SOI structure. According to an example embodiment, a portion of substrate is removed from the back side of a semiconductor die having a SOI structure and a backside opposite circuitry in a circuit side. Electrical connection is made to a portion of the circuitry within the die via a capacitive coupling arrangement. The electrical connection is used to obtain an electrical measurement correlated with circuitry logic states of the die that is used for analysis.Type: GrantFiled: January 5, 2001Date of Patent: September 16, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Jeffrey D. Birdsley, Brennan V. Davis, Daniel L. Stone, Michael R. Bruce, Rosalinda M. Ring