Abstract: A system and method are provided for profiling a structure in an integrated circuit to determine the structural dimensions. The system comprises a processor circuit that includes a processor electrically coupled to a local interface and a memory electrically coupled to the local interface, where the local interface comprises, for example, a data bus and associated control bus. The system further comprises a critical dimension scanning electron microscope having a signal output electrically coupled to the local interface and operating logic stored on the memory and executable by the processor. The operating logic comprises logic to execute a scan of a structure in an integrated circuit using the SEM, logic to store a first derivative waveform generated from the scan in the memory, and logic to generate a profile of the structure from the first derivative waveform.

Abstract: A system and method for bus arbitration. A computer system includes one or more buses for transferring data. Access to each bus is controlled by an arbitration unit. Various bus agents (i.e. peripherals) are coupled to the bus. Some bus agents are designated as normal-priority agents, while other bus agents are designated as high-priority bus agents. A high-priority bus agent may be a peripheral that is a latency-sensitive device. The arbitration unit may grant bus access to a normal-priority bus agent based on an arbitration scheme. When a high-priority bus agent requests access to the bus, the arbitration unit may cause the termination of access by the normal-priority bus agent. The high-priority bus agent is then granted access to the bus. When the high-priority bus agent has completed its use of the bus, the arbitration unit allows the normal-priority bus agent to regain access to the bus.

Abstract: A process for making semiconductor structures, and the resulting highly conductive semiconductor structures, includes using damascene process to form a structure with a thin adhesive layer and overlaying conductive layer. The highly conductive semiconductor structure has a thickness less than about 3000 Å, preferably less than about 2600 Å, and incorporates an adhesive layer that is preferably less than about 100 Å thick. Despite the reduced profile and topography of the structure, it is more conductive than prior structures, and provides a robust device.

Abstract: The present invention is generally directed to various methods for calibrating optical-based metrology tools. In one illustrative embodiment, the method comprises performing a metrology process on a specimen using an optical-based metrology tool to obtain optical characteristic data and comparing the obtained optical characteristic data to target optical characteristic data established for the specimen.

Abstract: A circuit and method for stopping a clock tree while maintaining PLL lock. A clock circuit includes a locked loop circuit and a clock tree distribution network. The locked loop circuit receives an input clock signal and generates a PLL output clock depending upon a feedback signal. The clock tree is coupled to the locked loop circuit and conveys the PLL output clock to a plurality of clocked circuit elements. The clock circuit further includes a gating circuit and a feedback delay circuit. The gating circuit is coupled between the locked loop circuit the clock tree distribution network and selectively inhibits the PLL output clock from clocking the clock tree distribution network. The feedback delay circuit provides the feedback signal, which represents a delayed version of the PLL output clock, during operation including when the gating circuit inhibits the PLL output clock from clocking the clock tree.

Abstract: A network switch in a packet switched network includes a plurality of network switch ports, each configured for sending and receiving data packets between a medium interface and the network switch. The network switch port includes an IEEE 802.3 compliant transmit state machine and receive state machine configured for transmitting and receiving network data to and from a medium interface, such as a reduced medium independent interface, respectively. The network switch port also includes a memory management unit configured for selectively transferring the network data between the transmit and receive state machines and a random access transmit buffer and a random access receive buffer, respectively. The memory management unit transfers the network data between the transmit and receive state machines and the respective buffers based on prescribed interface protocol signals between the memory management unit and the transmit and receive state machines.

Abstract: A method for reducing off-state leakage current of a MOSFET while promoting the formation of an epitaxial gate insulator layer between the substrate and gate stack includes implanting source/drain dopant into the substrate, and then forming a very thin epitaxial Silicon layer on the substrate by, e.g., molecular beam epitaxy. The high-k gate insulator layer is then deposited on the epitaxial layer, without an interfering native oxide or interfacial oxide being formed between the insulator layer and substrate, while establishing a very steep retrograde dopant profile and hence reducing off-state leakage current through the channel region.

Abstract: A method of fabricating a semiconductor device having contaminant-reduced Ca-doped Cu surfaces formed on Cu interconnects by cost-effectively depositing a Cu—Ca—X surface and subsequently removing the contaminant layer contained therein; and a device thereby formed. In the Cu—Ca—X surface, where contaminant X═C, S, and O, removal of the contaminant from such surface is achieved by (a) immersing the Cu interconnect surface into an electroless plating solution comprising Cu salts, Ca salts, their complexing agents, a reducing agent, a pH adjuster, and at least one surfactant for facilitating Ca-doping of the Cu interconnect material; and (b) annealing of the Cu—Ca—X surface under vacuum onto the underlying Cu interconnect material to form a Cu—Ca film on Cu interconnect structure, thereby producing a uniform Cu—Ca film (i.e., Cu-rich with 0.

Abstract: A method of patterning a layer of copper on a material surface includes providing a stamp having a base and a stamping surface and providing a copper plating catalyst on the stamping surface. The method can also include applying the stamping surface to the material surface, wherein a pattern of copper plating catalyst is applied to the material surface. The method can further include providing a copper solution over the copper plating catalyst, whereby a layer of copper is patterned on the material surface.

Abstract: A SOI substrate is preamorphized by ion implanting Xe prior to forming source/drain extensions and source/drain regions, thereby virtually eliminating or significantly reducing floating body effects. Other aspects comprise ion implanting a Xe2+ into a bulk silicon or SOI substrate to effect preeamorphization prior to forming source/drain extensions and regions having shallow junctions with reduced vertical and lateral straggle.

Abstract: The detection of a processing deviation in a multiple stage wafer processing system is achieved by assigning individual wafers a set of positional coordinates each time the wafer moves within the wafer processing system. In an example embodiment, a wafer is placed into a first processing stage and it is rotated to a certain angle of rotation. As the wafer moves from one processing stage to another the wafer is given a different angle of rotation; both the rotation angle and the wafer location are then recorded as a set of positional coordinates. The processed wafer is examined for surface deviations arising from variations in the processing parameters. The positional coordinates are used to develop a wafer movement map that aids in identifying the processing stage location where the deviation in the processing parameters occurred. An important advantage is the increased processing deviation traceability that the method brings to wafer processing.

Abstract: A method and an apparatus for performing process lifetime tracking of trench feature using optical analysis. A plurality of process steps is performed on a first set of semiconductor wafers. A manufacturing lifetime tracking of trench features is performed. A feedback corrective process is performed on a second set of semiconductor wafers based upon the lifetime tracking trench features. A feed-forward corrective process is performed on the first set of semiconductor wafers based upon the manufacturing lifetime tracking of trench features.

Abstract: A pellicle utilizes a film attached to a barrier layer above a substrate. The film is relatively transparent to radiation in the EUV range. The substrate and barrier layer are coupled to a periphery of the film and is exclusive of the center portion of the film. The pellicle can be manufactured by growing a relatively transparent film on a barrier layer that is grown on a substrate. The substrate and barrier layer are etched to expose a portion of the relatively transparent film.

Abstract: A semiconductor-on-insulator (SOI) device includes a buried insulator layer and an overlying semiconductor layer. Portions of the insulator layer are doped with the same dopant material, for example boron, as is in corresponding portions of the overlying surface semiconductor layer. A peak concentration of the dopant material may be located in the insulator material, or may be located in a lower portion of the surface semiconductor layer. The dopant material in the insulator layer may prevent depletion of dopant material from portions of the surface semiconductor layer, such as from channel portions of NMOS transistors.

Abstract: A low pass filter is configured for coupling home PNA network signals to a customer premises system having a two-wire European Installation Bus. The low pass filter uses an inductor having terminal ends connected to windings and configured in a non-compensating mode for generation of sufficient inductance for low pass filtering of the home PNA network signals from high frequency components of EIB signals generated by EIB bus coupling units. Use of an inductor having terminal ends connected to windings in a non-compensating mode enables the use of a smaller inductor core, such as a common mode choke or a ferrite bead toroid, that can fit within an EIB bus connector. Hence, existing EIB bus connectors can be replaced with improved coupling units having low pass filters that enable coupling of home PNA signals to the EIB bus. In addition, use of a toroid having windings in the non-compensating mode creates a closed loop within the toroid for flux induced by the windings, minimizing electromagnetic interference.

Abstract: A system-level (SLT) of a CPU device is performed in an automated test environment. Each device under test is automatically placed an SLT station and a test is performed at an initial operating speed. A CPU device which passes the test is then automatically removed and placed in a storage container based on that operating speed, also known as a rating (or rated) speed. If the device fails the test, however, then it remains in the test station and the operating speed of the station is adjusted until the device is able to pass the test. Once successful, the device is automatically removed and placed in a storage container based on the operating speed at which it finally was successful. A device which is unable to pass a system-level test at any speed is automatically removed and placed in a reject bin.

Abstract: The present invention provides for a method and an apparatus for control of final critical dimensions during processing of semiconductor wafers. A manufacturing run of semiconductor devices is processed. Metrology data from the processed semiconductor devices is acquired. A final critical dimension control adjustment process is performed using the acquired metrology data. A feedback/feed-forward modification process is performed in response to the final critical dimension control adjustment process.

Abstract: A method of synchronizing the generation and consumption of isochronous data in a computer system. In one embodiment, a computer system implements a method comprising providing a plurality of clocks to a plurality of isochronous sinks or sources configured to generate or consume the isochronous data, outputting a master clock signal to the plurality of isochronous sinks or sources, synchronizing said clocks to said master clock signal so that the generation or consumption of the isochronous data is synchronized to said master clock signal, outputting said master clock signal to an interrupt controller, and generating an interrupt based on said master clock signal, wherein a processor schedules one or more tasks that generate or consume data based on said interrupt. The isochronous sinks or sources may also be synched to a multiple of the master clock signal.

Abstract: A method and apparatus for fault handling in computer systems. In one embodiment, a first register is used to store an address which points to the top of a stack. The address stored in the first register may be updated during the execution of an instruction. A second register may be used to store an address previously first register. The contents of the second register may be kept unchanged until the retirement of the instruction that is currently executing. If a fault occurs during execution of the instruction, a microcode fault handler may perform routines that may clear the fault or those conditions which led to the fault. The microcode fault handler may also copy the contents of the second register back into the first register. Execution of the instruction may be restarted from the operation just prior to when the fault occurred. The program from which the instruction originated may then continue to run.

Abstract: A method of reducing electromigration in copper interconnect lines by restricting Cu-diffusion pathways along a Cu surface via doping the Cu surface with Zn from an interim copper-zinc alloy (Cu—Zn) thin film electroplated on the copper (Cu) surface from a stable chemical solution, and controlling the Zn-doping thereof, which also improves interconnect reliability and corrosion resistance, and a semiconductor device thereby formed. The method involves using interim reduced-oxygen Cu—Zn alloy thin films for forming an encapsulated dual-inlaid interconnect structure. The films are formed by electroplating a Cu surface via by electroplating, the Cu surface in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants; and annealing the interim electroplated Cu—Zn alloy thin films and a Cu-fill; and planarizing the interconnect structure.