Abstract: A novel method of automatically controlling thickness of a metal film during film deposition in a deposition chamber. The method involves producing an X-ray beam directed to the metal film deposited on a wafer in a deposition chamber, and detecting X-ray fluorescence of the metal film. The thickness of the metal film determined based on the detected X-ray fluorescence is compared with a preset value to continue deposition if the determined thickness is less than the preset value. Deposition is stopped when the determined thickness reaches the preset value.
Abstract: The present invention is directed to a method of controlling the formation of metal layers. In one illustrative embodiment, the method comprises depositing a layer of metal above a structure, irradiating at least one area of the layer of metal, and analyzing an x-ray spectrum of x-rays leaving the irradiated area to determine a thickness of the layer of metal. In further embodiments of the present invention, a plurality of areas, and in some cases at least five areas, of the layer of metal are irradiated. The layer of metal may be comprised of, for example, titanium, cobalt, nickel, copper, tantalum, etc.
Type:
Grant
Filed:
April 30, 2001
Date of Patent:
August 26, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Paul R. Besser, Paul L. King, Susan Kim
Abstract: The present invention provides a method and system for polishing a wafer surface. The method and system comprises determining whether a thickness of the wafer surface is uniform while the wafer surface is being polished, and adjusting the polishing process while the wafer surface is being polished based on the determination of whether the thickness of the wafer surface is uniform. Through the use of the method and system in accordance with the present invention, in-situ adjustments can be made to the CMP polishing process while the wafer is actually being polished. This results in a substantial improvement in polishing uniformity.
Abstract: When a riser card is connected to a computer system motherboard, a storage device on the riser card will contain configuration data permitting the computer system to configure any peripheral device on the riser card. The configuration data will be treated by the BIOS in the computer system as a virtual add-on ROM thereby allowing it to execute and initialize any and all PCI configuration spaces associated with the riser card peripheral devices.
Type:
Grant
Filed:
February 4, 2000
Date of Patent:
August 26, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Timothy C. Maleck, Charles R. Boswell, Brian Barnes
Abstract: Devices and methods for releasing an integrated circuit from its container are provided. The devices include a handle portion and a gripping portion. The gripping portion has one or more notches that are used to engage an integrated circuit container pin. In one aspect, the gripping portion is used to engage the container pin, and downward pressure is applied to the handle portion to remove the pin. In another aspect, the gripping portion is used to engage the container pin, and the handle portion is twisted to remove the pin.
Abstract: A method for removing polysilicon from isolation regions on a substrate during semiconductor fabrication is disclosed. The method includes depositing a layer of polysilicon over the substrate, and depositing at least one dielectric layer over the polysilicon. The method further includes polishing the polysilicon from the isolation regions, wherein the dielectric layers act as a polishing stop, resulting in regions of polysilicon that are self-aligned to the trench isolation regions.
Type:
Grant
Filed:
May 15, 2002
Date of Patent:
August 26, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Jack F. Thomas, Unsoon Kim, Krishnashree Achuthan
Abstract: In a first aspect of the present invention, a flash memory array is disclosed. The flash memory array comprises a substrate comprising active regions, wherein the active regions are defined by a layer of nitride, the layer of nitride including a top surface. The flash memory array further comprises shallow trenches in the substrate, each of the shallow trenches including a layer of oxide, the layer of oxide having a top surface, wherein the top surface of the layer of oxide and the top surface of the layer of nitride are on substantially the same plane and channel areas wherein the occurrences of polyl stringers in the channel areas is substantially reduced. In a second aspect of the present invention, a method and system for fabricating a flash memory array is disclosed. The method comprises the steps of providing a layer of nitride over a substrate, forming trenches in the substrate and then growing a layer of oxide in the trenches. Finally, the layer of oxide is polished back.
Type:
Grant
Filed:
May 2, 2000
Date of Patent:
August 26, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Maria C. Chan, Hao Fang, Mark S. Chang, Mike Templeton
Abstract: A semiconductor device may include a substrate and an insulating layer formed on the subtrate. A fin may be formed on the insulating layer and may include a number of side surfaces and a top surface. A first gate may be formed on the insulating layer proximate to one of the number of side surfaces of the fin. A second gate and may be formed on the insulating layer separate from the first gate and proximate to another one of number of side surfaces of the fin.
Abstract: A system and a method are disclosed for providing a power saving mode during reading a memory device. A new memory content is read from the memory and, before being put at the memory output bus, is compared with the previously read memory content, which is currently on the output bus of the memory device. If the result of the comparison indicates that more than half of the memory output bits have to be toggled in order to put the new memory content on the memory output bus, the new data is inverted internally in order to reduce the number of output pins toggles. Then, the memory device sends a signal to the microprocessor or microcontroller indicating that the new data is inverted, and that the new data has to be inverted back before being put on the memory output bus.
Abstract: A fully depleted silicon on insulator (SOI) field effect transistor (FET) includes a gate positioned above a channel region and an aligned back gate positioned below the channel region and the buried oxide later. Alignment of the back gate with the gate is achieved utilizing a disposable gate process and retrograde doping of the backgate.
Abstract: Computer system configuration resources include first and second control circuits in respective first and second integrated circuits. A communication link, which transfers data over a plurality of logical pipes, connects the two integrated circuits. Configuration of the link utilizes a link bridge that includes upstream (located closest to the CPU) configuration registers that are within the first control circuit and downstream ((located farthest from the CPU) configuration registers within the second control circuit. A link header, which includes upstream data for the first control circuit and down stream data for the second control circuit, is used to initialize the link. The upstream and downstream data may include information specifying the size of the communication link.
Abstract: A method of manufacturing a semiconductor device includes forming a first level, forming a first barrier layer over the first level, forming a dielectric layer over the first barrier layer, forming an opening through the dielectric layer, etching the first barrier layer, and filling the opening with metal to form a first metal feature. The first barrier level is etched using CHF3 and CH3F. Additionally, the first barrier layer can be formed from silicon nitride.
Type:
Grant
Filed:
March 16, 2001
Date of Patent:
August 26, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Lynne A. Okada, Fei Wang, Calvin T. Gabriel
Abstract: A method is provided, the method comprising forming a first conductive structure, and forming a first dielectric layer above the first conductive structure. The method also comprises forming a first opening in the first dielectric layer above at least a portion of the first conductive structure, the first opening having sidewalls, and densifying the sidewalls.
Type:
Grant
Filed:
July 10, 2001
Date of Patent:
August 26, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Eric M. Apelgren, Christian Zistl, Jeremy I. Martin, Paul R. Besser, Fred Cheung
Abstract: A system and method are presented for selectively conditioning a surface of a polishing pad of a CMP apparatus in order to achieve a desired surface profile of a semiconductor wafer. The semiconductor wafer may be subjected to a CMP operation using the CMP apparatus following the conditioning. The present CMP apparatus includes a polishing pad having an underside surface mechanically coupled to a substantially planar surface of a platen, an abrasive surface, and a measurement system. The platen and abrasive surface may be rotatable about respective rotational axes. The present conditioning method includes selecting a region of an upper “polishing” surface of the polishing pad (e.g., a CMP region) encircling a rotational axis of the platen and bounded by first and second radial distances from the rotational axis of the platen.
Type:
Grant
Filed:
September 25, 2001
Date of Patent:
August 19, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Rigel G. Arcayan, Jose M. Pineda-Garcia, Michael K. Burleson
Abstract: The present invention provides for a method and an apparatus for controlling manufacturing processes using a hierarchical system. A first lot of semiconductor devices is processed using a first set of control input parameters. The first set of control input parameters is stored in one of a plurality of hierarchical levels, the first set of control input parameters being available for processing of a second lot of semiconductor devices. Process data is acquired from the processing of the first lot of semiconductor devices. A second set of control input parameters is determined for a subsequent lot of semiconductor devices based upon the acquired process data. The second set of control input parameters is stored in one of a plurality of hierarchical levels, the first and second sets of control input settings being available for processing of a third lot of semiconductor devices.
Type:
Grant
Filed:
August 10, 1999
Date of Patent:
August 19, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Anthony J. Toprac, William J. Campbell, Christopher A. Bode
Abstract: A method and system providing single point high spatial and timing resolution for photoemission microscopy of an integrated circuit. A microscope having an objective lens forming a focal plane is arranged to view the integrated circuit, and an aperture element having an aperture is optically aligned in the back focal plane of the microscope. The aperture element is positioned for viewing a selected area of the integrated circuit. A photo-diode optically aligned with the aperture to detect photoemissions when test signals are applied to the integrated circuit.
Abstract: One aspect of the invention relates to forming a high-k dielectric layer comprising a Group IVB metal compound, especially HfO2, HfSixOy or HfSixOyNz. According to the invention, these compounds are formed by molecular layer deposition. According to another aspect of the invention, molecular layer deposition is used to add silicon oxynitride to the dielectric. The silicon oxynitride provides a barrier to diffusion of dopants from the gate to the channel region.
Abstract: A method is provided, the method comprising programming a silicide fuse by passing a current through the silicide fuse while substantially simultaneously irradiating the silicide fuse with a laser.
Abstract: A method for repairing an isolation dielectric damaged during a semiconductor fabrication process is disclosed in which a hard mask material is used to pattern a first material, the first material having openings therein exposing isolation regions comprising a first isolation dielectric layer. The method includes etching the hard mask material from the first material, wherein the etch creates gouges in the first isolation dielectric layer, and depositing a second layer of isolation dielectric over the first material, wherein the second isolation dielectric layer fills the gouges in the first isolation dielectric layer. The method further includes polishing on the second layer of isolation dielectric to remove the second layer of isolation dielectric from the first material.
Type:
Grant
Filed:
June 6, 2002
Date of Patent:
August 19, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Unsoon Kim, Dawn M. Hopper, Yider Wu, Krishnashree Achuthan
Abstract: An inspection tool or inspection system can be utilized to determine whether the appropriate pattern is on a reticle. The reticle can be associated with EUV lithographic tools. The system utilizes at least two wavelengths of light. The light is directed to the reticle at the at least two wavelengths of light and detected by a detector. The image associated with the first wavelength is subtracted from or otherwise processed with respect to the image associated with the second wavelength to improve contrast ratio.
Type:
Grant
Filed:
February 1, 2001
Date of Patent:
August 19, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Bruno M. La Fontaine, Harry J. Levinson, Jeffrey A. Schefske