Abstract: The present invention is a method and system for processing a semiconductor device, the semiconductor device comprising at least two gate stacks and a spacer gap. The method and system comprise utilizing a spin-on technique at the transistor device level to provide an oxide spacer in the spacer gap and then curing the semiconductor device at a temperature above approximately 450° C. Through the use of a system/method in accordance with the present invention, the voids that are created in the spacer gaps during conventional semiconductor processing are eliminated. Furthermore, the oxide spacers posses the high quality characteristics that are typically provided through the use of the conventional CVD methodology. Accordingly, as a result of the use of the system/method in accordance with the present invention, the MOSFET oxide spacers are strengthened, which increases the reliability of the semiconductor device.

Abstract: A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.

Abstract: A method and apparatus for scheduled controller execution based upon impending lot arrival at a processing tool in an APC framework. It is determined which lot of processing pieces that is to be processed by a processing tool and the lot of processing pieces is retrieved from a remote location. A predefined set of calculations is initiated relating to the operation of the processing tool in anticipation of delivering the lot of processing pieces to the processing tool. The lot of processing pieces is delivered to the processing tool, and the processing pieces are processed by the processing tool using the predefined set of calculations.

Abstract: A solder bump structure and a method for forming the same are disclosed. Over a contact pad a first and a second metal film are deposited, wherein the second metal film is patterned prior to the deposition of a solder bump material such that an opening isolates an inner region of the second metal film from an outer region of the second metal film. The solder material deposited on the inner region and, at least partially, in the opening serves as an etch stop for a subsequent removal of the outer region.

Abstract: A method and system for providing a low-level recovery of data on a communication network that provides an immediate negative acknowledgement of a data packet that contains bit errors, as determined by a receiving node on the network. The data packets contain two error detection mechanisms, with the first error detection mechanism being used by the receiving node to determine whether the data packet is uniquely addressed to that receiving node. When this is determined by the receiving node, the data payload is then checked to determine whether it contains a bit error. When an error is detected, the receiving node immediately sends out a negative acknowledgement, prior to the normal interframe spacing provided in network protocols, so that the transmitting node becomes aware that the data packet was not properly received at the receiving node. The transmitting node can then retransmit the data packet.

Abstract: A method for correcting overerasure in a multi-bit memory device. A sector of multi-bite memory cells in the device is erased and verified. After erase and verification, the overerased memory cells are soft programmed and verified to correct for overerasure. A soft programming pulse with a Vg to Vd ratio (Vg/Vd) greater than or equal to two is used.

Abstract: A method for characterizing a misprocessed wafer includes providing a wafer having a grating structure; illuminating at least a portion of the grating structure; measuring light reflected from the grating structure to generate a reflection profile; and characterizing a misprocessed condition of the wafer based on the reflection profile. A metrology tool adapted to receive a wafer having a grating structure includes a light source, a detector, and a data processing unit. The light source is adapted to illuminate at least a portion of the grating structure. The detector is adapted to measure light reflected from the grating structure to generate a reflection profile. The data processing unit is adapted to characterize a misprocessed condition of the wafer based on the reflection profile.

Abstract: Reliable contacts/vias are formed by filling an opening in a dielectric layer with W and laser thermal annealing to eliminate or significantly reduce voids. Embodiments include depositing W to fill a contact/via opening in an interlayer dielectric, laser thermal annealing in N2 to elevate the temperature of the W filling the contact/via opening and reflow the W thereby eliminating voids. Embodiments include conducting CMP either before or subsequent to laser thermal annealing.

Abstract: The present invention provides SEM calibration standards, and associated SEM systems and SEM calibration methods, that are self-cleaning with respect to electron beam deposited carbon. The calibration standards have coatings containing a transition metal oxide. The coatings facilitate oxidation of deposited carbon, whereby carbon buildup can be stopped or reversed. By providing a mechanism to mitigate carbon buildup, calibration standards provided by the present invention achieve high accuracy, high durability, and low cost.

Abstract: Semiconductor die analysis is enhanced using a system that is adapted to perturb a die in a test chamber and to detect a response from the die to the perturbation. According to an example embodiment of the present invention, a semiconductor die analysis system includes a test chamber and a docking arrangement adapted to dock with the test chamber. A die is held in the docking arrangement and is presented inside of the test chamber when the docking arrangement is docked with the chamber. Two or more perturbation devices are used to perturb the die, and controller is adapted to control the perturbation. A data acquisition arrangement receives data from the die in response to the perturbation, and the data is used for analyzing the die.

Abstract: An integrated circuit die coupled to a package substrate and having circuitry in a circuit side opposite a back side is etched in a manner that inhibits the erosion of underfill material that is used around the periphery of the die and between the die and the package substrate. According to an example embodiment of the present invention, a protective coating adapted to resist etch chemicals is formed over the underfill material. The die is then etched using an etch chemistry that, absent the protective coating, would erode the underfill material. In this manner, etch chemistries that would harm the die, or even be unusable can be used to etch the die. In addition, problems associated with the underfill being eroded, such as die chipping, can be avoided.

Abstract: A method and system for insulating a lower layer of a semiconductor device from an upper layer of the semiconductor device is disclosed. The method and system include providing an interlayer dielectric on the lower layer. The interlayer dielectric is capable of gap filling while using only species of relatively low mobility. The method and system also include planarizing a surface of the interlayer dielectric.

Abstract: A novel method of flow control in a multiport data switching system having a decision making engine for controlling data forwarding between receive ports and at least one transmit port. Data blocks representing received data packets are placed in a plurality of data queues to be processed by the decision making engine. The data queues allocated to the receive ports are monitored to produce a flow control threshold signal for a selected data queue to indicate a heavy traffic condition of a receive port corresponding to the selected data queue. For example, the flow control threshold signal may indicate that the receive port is close to an overflow condition. Monitoring of a selected data queue may be performed by comparing a write pointer indicating a memory location for writing the data blocks into the selected data queue with a read pointer indicating a memory location for reading the data blocks from the selected data queue.

Abstract: A method for monitoring temperature in a thermal processing system includes the steps of depositing (105) a cobalt film (104) on a semiconductor substrate (103) and performing thermal processing (108) on the substrate (103) to generate a cobalt silicide film (109). The method further includes measuring (110) a resistance characteristic of the cobalt silicide (109) and determining a temperature of the thermal processing using the resistance characteristic (112).

Abstract: There is provided a method for forming a photoresist layer for photolithographic applications which has increased structural strength. The photoresist layer is exposed through a mask and developed. The photoresist layer is then treated to change its material properties before the photoresist layer is dried. Also provided are a semiconductor fabrication method employing a treated photoresist and a composition for a treatable photoresist.

Abstract: A system and method is provided for applying a developer to a photoresist material wafer disposed on a semiconductor substrate. The developer system and method employ a developer plate having a plurality of a apertures for dispensing developer. Preferably, the developer plate has a bottom surface with a shape that is similar to the wafer. The developer plate is disposed above the wafer and substantially and/or completely surrounds the top surface of the wafer during application of the developer. A small gap is formed between the wafer and the bottom surface of the developer plate. The wafer and the developer plate form a parallel plate pair, such that the gap can be made small enough so that the developer fluid quickly fills the gap. The developer plate is disposed in very close proximity with respect to the wafer, such that the developer is squeezed between the two plates thereby spreading evenly the developer over the wafer.

Abstract: A line predictor caches alignment information for instructions. In response to each fetch address, the line predictor provides information for the instruction beginning at the fetch address, as well as alignment information for up to one or more additional instructions subsequent to that instruction. The line predictor may include a memory having multiple entries, each entry storing up to a predefined maximum number of instruction pointers and a fetch address corresponding to the instruction identified by a first one of the instruction pointers. Since the line predictor provides alignment information from one entry per fetch, the line predictor may provide a flow control mechanism for the initial portion of the pipeline within a microprocessor. Each entry may store combinations of instructions which the hardware within the pipeline may handle without creating stalls resulting from the combinations.

Abstract: The present invention relates to illuminating an interior portion of a processing chamber in a semiconductor processing system. A light emitting diode is located in the chamber to illuminate the interior of the chamber to facilitate viewing the interior of the chamber.

Abstract: A method of manufacturing a semiconductor device, comprising the steps of: (a) providing a semiconductor substrate having a surface; (b) forming a gate oxide layer on at least a portion of the surface and including an interface therewith, the gate oxide layer comprising a high-k dielectric oxide including a plurality of interface traps at the interface; (c) forming a gate electrode layer on at least a portion of the gate oxide layer; and (d) laser thermal annealing the high-k gate oxide layer to de-activate the interface traps without incurring formation of a low-k dielectric oxide layer at the interface.

Abstract: Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices are fomxed by a salicide process wherein a blanket nickel layer is formed in contact with the exposed portions of the substrate surface adjacent the sidewall spacers, the top surface of the gate electrode, and the sidewall spacers. Embodiments include forming the blanket layer of nickel is formed by the sequential steps of: (i) forming a layer of nickel by sputtering with nitrogen gas; and, (ii) forming a layer of nickel by sputtering with argon gas. The two step process for forming the blanket layer of nickel advantageously prevents the formation of nickel silicide on the outer surfaces of the insulative sidewall spacers.