Abstract: A method of programming that includes programming a fresh memory cell with a substrate that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. Baking the programmed fresh cell causing a charge loss in the channel while the remaining charge within the channel is distributed more locally at the first region when compared to the distribution of charge prior to the baking.

Abstract: Device leakage due to spacer undercutting is remedied by depositing a BPSG, SA-CVD oxide liner and flowing it into the undercut regions, followed by gap filling with a P-doped HDP oxide layer. Embodiments include depositing a BPSG, SA-CVD oxide liner containing 4 to 6 wt.% boron, at a thickness of 1,000 Å to 1,800 Å, over closely spaced apart non-volatile transistors and heating during or subsequent to deposition to flow the BPSG, SA-CVD oxide liner into the undercut regions of the sidewall spacers of the gate stacks. Gap filling is then completed by depositing the layer of P-doped HDP at a thickness of 6,000 Å to 10,000 Å.

Abstract: In an in situ damascene metallization process employing a barrier layer between the metal and the dielectric, the generation of voids, especially at the bottom of vias, can be significantly reduced or even completely avoided by maintaining the surface temperature below a critical temperature during deposition of the barrier material.

Abstract: In one illustrative embodiment, an apparatus for controlling a translation lookaside buffer is provided. The apparatus comprises a translation unit, a buffer, and a comparator. The translation unit is adapted to initiate a table walk process to convert a virtual memory address to a physical address. The buffer is adapted to store pending memory access requests previously processed by the translation unit. The comparator is adapted to determine if a physical address generated by the table walk process of the translation unit conflicts with a physical address of at least one of the pending memory access requests, and deliver a control signal to the translation unit for canceling the table walk process in response to determining that a conflict exists.

Abstract: A method for resolving data to one stored level of N possible stored levels in a multi-level memory includes receiving an access address associated with a memory location of the multi-level memory and applying an ascending staircase read voltage to a word line associated with the access address. The method further includes detecting a sense signal produced on a sense line associated with the access address in response to the stored level and a value of the staircase read voltage, for each value of the ascending staircase read voltage, storing data responsive to the sense signal, and after application of a final value of the ascending staircase read voltage, producing an N-bit value corresponding to the one stored level stored in the memory location.

Abstract: One aspect of the present invention relates to a method for reducing resist residue defects on a wafer structure. The method involves providing a semiconductor structure having a photoresist, the photoresist comprising open areas and circuit areas thereon; irradiating the open areas and circuit areas through a first photomask with a first energy dose to effect an image-wise pattern in the photoresist; irradiating the open areas of the photoresist through a second photomask with a second energy dose; and developing the photoresist.

Abstract: In one embodiment, the present invention relates to a method of forming a silicon-on-insulator substrate, involving the steps of providing a first silicon substrate and a second silicon substrate; surface modifying at least one of the first silicon substrate and the second silicon substrate by forming a pattern thereon; forming a first insulation layer over the first silicon substrate to provide a first structure and a second insulation layer over the second silicon substrate to provide a second structure; bonding the first structure and the second structure together so that the first insulation layer is adjacent the second insulation layer; and removing a portion of the first or second silicon substrate thereby providing the silicon-on-insulator substrate.

Abstract: An edge bead removal system and method is provided that employs a nozzle for applying edge bead removal solvent to an edge bead of a photoresist material layer disposed on a wafer. The nozzle includes a liquid chamber that can be connected to a supply of edge bead removal and an air supply chamber that can be connected to a supply of air. The supply of air is isolated from the liquid supply chamber during application of the edge bead removal solvent and communicates via the air supply chamber to the liquid supply chamber after application of the edge bead removal solvent thus removing any droplets of edge bead removal solvent remaining in the nozzle tip. A system is also provided that includes an absorbent material that moves from a rest position, during application of the edge bead removal solvent, to an absorbing position that removes or catches any droplets of edge bead removal solvent remaining on the nozzle tip after application of the edge bead removal solvent is completed.

Abstract: A method is provided, the method comprising planarizing a dielectric layer disposed above a structure layer, exciting surface plasmons in a conductive film disposed in the dielectric layer and detecting photons reflected from the conductive film to determine a change in a surface plasmon resonant angle. The method also comprises determining a thickness of the dielectric layer from the change in the surface plasmon resonant angle.

Abstract: Shallow trench isolation techniques are disclosed in which a thin nitride layer is formed on a semiconductor substrate, and a trench is formed through the nitride layer and into the semiconductor substrate, which is then filled. The wafer is then planarized using a fixed-abrasive CMP process to mitigate or avoid step height in the shallow trench isolation process. The nitride layer is then removed following planarization.

Abstract: A method and apparatus for replacing dense via arrays in shrunk, electronic device designs involves identifying vias on the same node within the electronic device design. Once vias are identified as on the same node, the combined area of the vias is calculated. Based upon the combined area of the identified vias, a determination of how many new, larger vias to create is made. New vias that are larger than the originally identified vias are created in such a number that the total area of the new vias at least equals the combined area of the originally identified vias. The new via array, having greater spacing between individual vias than the original via array, is used to replace the original via array within the electronic device design.

Abstract: A method for characterizing features includes measuring a dimensional characteristic of a first grating structure; illuminating at least a portion of a first feature and the first grating structure, the first feature being formed over at least a portion of the first grating structure; measuring light reflected from the illuminated portion of the first feature and the first grating structure to generate a reflection profile; selecting at least one reference reflection profile based on the measured dimensional characteristic of the first grating structure, comparing the generated reflection profile to the selected reference reflection profile; and determining a characteristic of the first feature based on the comparison between the measured reflection profile and the selected reference reflection profile.

Abstract: A network interface controller arrangement and a method of testing a memory arrangement uses a register to hold failing information from a memory built-in self test (MBIST). The register is accessible to a processor through a bus interface of the network interface controller. The processor performs a read operation through the bus interface upon the completion of an MBIST to examine the failing information.

Abstract: The present invention is generally directed to a transistor having a gate stack comprised of a metal, and a method of making same. In one illustrative embodiment, the transistor is comprised of a gate stack comprised of a gate insulation layer positioned above a semiconducting substrate, a layer of silicon positioned above the gate insulation layer, a layer of adhesion material positioned above the layer of silicon, a layer of metal positioned above the layer of adhesion material, and a plurality of source/drain regions formed in the substrate adjacent the gate stack.

Abstract: A method for controlling a manufacturing system includes processing workpieces in a plurality of tools; initiating a baseline control script for a selected tool of the plurality of tools; providing context information for the baseline control script; determining a tool type based on the context information; selecting a control routine for the selected tool based on the tool type; and executing the control routine to generate a control action for the selected tool. A manufacturing system includes a plurality of tools adapted to process workpieces, a control execution manager, and a control executor. The control execution manager is adapted to initiate a baseline control script for a selected tool of the plurality of tools and provide context information for the baseline control script.

Abstract: A semiconductor stack is provided. The semiconductor stack is comprised of a first semiconductor device, a second semiconductor device, and a socket. The first semiconductor device has a plurality of pins extending therefrom and arranged in a first preselected pattern. The socket is adapted to receive the plurality of pins. The second semiconductor device is disposed between the socket and the first semiconductor device and includes a die, a casing, and a plurality of electrical connections. The casing extends about the die and defines a plurality of openings extending therethrough. The openings are arranged in a first preselected pattern to receive the pins of the first semiconductor device. The plurality of electrical connections are disposed in at least a portion of the plurality of openings. The electrical connections are adapted to electrically communicate with the pins of the first semiconductor device inserted therein and the die.

Abstract: A model-based approach for generating an etch pattern to decrease topographical uniformity involves placing reverse dummy features (50, 52, 70) in a region of a semiconductor substrate (40, 60) according to the topography of the region and adjacent regions. The reverse dummy features are placed inconsistently over the semiconductor substrate (40, 60) because the need for reverse dummy features is inconsistent and varies from design to design. In one embodiment, the reverse dummy features (50, 52, 70) having varying widths are placed with varying spacing between them and are placed in different regions. The determination of location, size and spacing of the reverse dummy features (50, 52, 70) is determined based upon the uniformity effect over the entire semiconductor die and may be used in conjunction with the placement of printed dummy features.

Abstract: An integrated circuit fabrication process for patterning features at sub-lithographic dimensions is disclosed herein. The process includes sequentially exposing a of a film of arylalkoxysilane with a photobase generator, and catalytic amount of water coated on top of a conventional lipophilic photoresist layer provided over a substrate and exposed to a radiation at a first and a second lithographic wavelengths. The first lithographic wavelength is shorter than the second lithographic wavelength. Exposure to the first lithographic wavelength causes a self-aligned mask to form within the photoresist layer.

Abstract: Various circuit devices incorporating junction-traversing dislocation regions and methods of making the same are provided. In one aspect, a method of processing is provided that includes forming an impurity region in a device region of a semiconductor-on-insulator substrate. The impurity region defines a junction. A dislocation region is formed in the device region that traverses the junction. The dislocation region provides a pathway to neutralize charge lingering in a floating body of a device.

Abstract: A method, system and computer program product to isolate information related to performing a manufacturing process, called a configuration document, from the context in which the information is used. A context/configuration association can be independently established between a process context and a context-free configuration document including instructions for performing a manufacturing process. Because the context/configuration association is independent of both the process context and the context-free configuration document, the context/configuration association can be independently reviewed and approved without affecting other process contexts or configuration documents.