Abstract: An electrostatic lens with glassy graphite electrodes for use in an ion implanter is disclosed. The graphite electrodes have been manufactured to be substantially smooth (glassy) such that irregularities on the surface grain of the graphite, for example peaks or apexes, are no longer present. In an embodiment, employing polished graphite electrostatic lens electrodes does not require the time-consuming conditioning operations under vacuum that are typically needed with conventional graphite electrodes, and thus offers the advantage of increased uptime for an ion implantation system. In addition, because surface irregularities are not present to serve as discharge points for electrostatic buildup, the use of glassy graphite electrodes as disclosed offers the advantage of electrostatic discharge reduction.

Abstract: A method of manufacturing an integrated circuit may include the steps of annealing a gate structure and a halo section disposed over a substrate using a first temperature, implanting dopants to form drain and source regions, and annealing drain and source regions at a second temperature. The second temperature is substantially less than the first temperature.

Abstract: A method is provided that comprises forming a copper seed layer on a workpiece and measuring the uniformity of the copper seed layer on the workpiece. The method further comprises applying the uniformity measurement to modify processing to form a copper layer having a desired uniformity profile for increased planarization in subsequent planarizing.

Abstract: An asymmetric semiconductor device and a method of making a pair of the asymmetric devices. The semiconductor device includes a layer of semiconductor material having a source and a drain, and a dual work function gate disposed on the layer of semiconductor material to define a channel interposed between the source and the drain.

Abstract: A method of fabricating a feature of an integrated circuit in a layer of material includes providing a layer of photoresist over the layer of material; exposing the layer of photoresist to a source of radiation to form an aperture therein, wherein the aperture has a wall; providing a self-assembled monolayer on at least a portion of the wall, wherein the self-assembled monolayer masks a portion of the layer of material; and etching the layer of material to form a feature, whereby the self-assembled monolayer prevents the portion of the layer of material from being etched.

Abstract: A method and an apparatus for performing trench depth analysis in semiconductor device manufacturing. A first processing on at least one semiconductor wafer is performed. Optical trench data is acquired from the processed semiconductor wafer. An optical trench analysis, based upon the optical trench data, is performed. A corrective feedback step is performed during a second processing of the semiconductor wafer in response to the optical trench analysis.

Abstract: A system for regulating the time and temperature of a development process is provided. The system includes one or more light sources, each light source directing light to one or more gratings being developed on a wafer. Light reflected from the gratings is collected by a measuring system, which processes the collected light. Light passing through the gratings may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the progress of development of the respective portions of the wafer. The measuring system provides progress of development related data to a processor that determines the progress of development of the respective portions of the wafer. The system also includes a plurality of heating devices, each heating device corresponds to a respective portion of the developer and provides for the heating thereof. The processor selectively controls the heating devices so as to regulate temperature of the respective portions of the wafer.

Abstract: A method and apparatus for automatically verifying whether a network interface is transmitting frame data properly. Frame data stored in host memory is transmitted to the network interface and to a transmit data checker. The network interface receives, processes and transmits the frame data. The processed frame data is transmitted to a network media and to the transmit data checker. The transmit data checker compares the frame data from the host memory with the processed frame data from the network interface and generates an indicator signal. The indicator signal indicates whether the network interface is transmitting processed frame data properly. The indicator signal is sent to a display which displays the result. The transmit data checker includes a timer for determining the processing time of the network interface. The timer measures the time between reception of the frame data from the host memory and the reception of the transmitted data.

Abstract: A buried interconnect can be incorporated into the starting semiconductor on insulator wafer during the early stages of the circuit fabrication process flow for use with semiconductor devices. The buried interconnect provides an additional interconnect layer enabling an overall reduction in the silicon real estate occupied by interconnections. The buried interconnect has low resistance and can prevent the formation of unwanted PN junctions through the use of silicides. The buried interconnect and its fabrication method include an S0I wafer that has an oxidation layer formed on top of a semiconductor layer by oxidation, followed by an nitride layer formed on top of the oxide layer which then is selectively etched to form two trenches with regions of different depths. Some regions of the trenches are etched to remove all of the semiconductor layer in the trench to expose the buried oxide layer. In other regions, a thin layer of semiconductor is left at the bottom of the trenches.

Abstract: A non-volatile memory device includes a number of memory cells, parts of which are delineated by insulators. The insulators each include both a lower trench-fill insulator portion in a trench in the substrate, and an upper protruding portion that protrudes from the substrate. Between each pair of adjacent protruding insulator portions there is a pair of floating gates, the floating gates in contact with respective of the protruding insulator portions. There is a space or gap between the floating gates, such that a portion of a control gate enters therein, separated from the substrate by only an interpoly dielectric such as an oxide-nitride-oxide (ONO) stack, and a tunnel oxide. By storing charge on the floating gates, the conductivity of a channel between the floating gates may be altered. For example, conductivity through the channel may be “pinched off” by storing charge on the floating gates.

Abstract: A metbod for perforning a wafer-less qualification of a processing tool includes creating a wafer-less qualification model for the processing tool. Qualification data is generated from the processing tool iiiring a wafer-less qualification process. The qualification data is compared with the wafer-less qualification model. The processig tool is determined to be operating in a predefined state based on the comparison of the qualification data with the wafer-less qualification model.

Abstract: A method of forming an etch mask includes patterning a top surface of a photoresist layer, carbonizing the patterned top surface of the photoresist layer and selectively removing portions of the photoresist layer. Portions of the photoresist layer under the carbonized areas remain. A substrate or a layer above substrate can be etched or processed in accordance with the mask formed from the photoresist layer.

Abstract: A comparator comprises a switching means for supplying two different threshold voltages to the comparator upon a first and a second control signal, respectively. The second control signal is enabled by a rising or a falling edge of the comparator output that is coupled to a control means providing the second control signal. The time interval that a varying input signal requires to change its amplitude crossing and in between the two threshold voltages can thus be detected by two subsequent rising or falling edges of the comparator output without the adverse influence of the comparator's meta-stability.

Abstract: A circuit comprises an active filter with linear elements and a tuning circuit with linear elements of the same type as the filter circuit. A backward counter generates a count value that represents a time constant of the tuning circuit. The initial value of the backward counter contains information concerning the relationship between the time constant of the filter circuit and the tuning circuit. A decoder creates a digital code responsive to the count value which is used to switch an array of linear elements in order to tune the time constant of the filter to approximately a desired design value.

Abstract: A method of eliminating voids in the interlayer dielectric material of 0.18-&mgr;m flash memory semiconductor devices and a semiconductor device formed by the method. The present invention provides a method for eliminating voids in the interlayer dielectric of a 0.18-&mgr;m flash memory semiconductor device by providing a first BPTEOS layer, using a very low deposition rate and having a thickness in a range of approximately 3 kÅ; and providing a second BPTEOS layer, using a standard deposition rate and having a thickness in a range of approximately 13 kÅ, wherein both layers have an atomic dopant concentration of approximately 4.5% B and approximately 5% P. This two-step deposition process completely eliminates voids in the ILD for a 0.5-&mgr;m distance (gate-to-gate) as well as 0.38-&mgr;m distance (gate-to-gate) which is the future flash technology.

Abstract: A system and method for bus arbitration. A computer system includes one or more buses for transferring data. Access to each bus is controlled by an arbitration unit. Various bus agents (i.e. peripherals) are coupled to the bus. Some bus agents are designated as normal-priority agents, while other bus agents are designated as high-priority bus agents. A high-priority bus agent may be a peripheral that is a latency-sensitive device. The arbitration unit may grant bus access to a normal-priority bus agent based on an arbitration scheme. When a high-priority bus agent requests access to the bus, the arbitration unit may cause the termination of access by the normal-priority bus agent. The high-priority bus agent is then granted access to the bus. When the high-priority bus agent has completed its use of the bus, the arbitration unit allows the normal-priority bus agent to regain access to the bus.

Abstract: A memory circuit employed in a memory device is disclosed. According to one embodiment, the memory circuit comprises a first memory cell and a second memory cell. The first memory cell has a drain terminal connected to a bit line, which is connected to a sensing circuit. The first memory cell also has a control gate connected to a word line. The second memory cell also has a drain terminal connected to the bit line. The second memory cell has its control gate coupled to ground. The memory circuit supplies a source voltage greater than a ground voltage to a source terminal of the first memory cell and to a source terminal of the second memory cell such that the gate-to-source voltage of the second memory cell is less than the threshold voltage of the second memory cell.

Abstract: A silicon oxide insulator (SOI) device includes an SOI layer supported on a silicon substrate. A body region is disposed on the SOI layer, and the body region is characterized by a first conductivity type. Source and drain regions are juxtaposed with the body region, with the source and drain regions being characterized by a second conductivity type. A transition region is disposed near the body region above the SOI layer, and the conductivity type of the transition region is established to be the first conductivity type for suppressing floating body effects in the body region and the second conductivity type for isolating the body region. An ohmic connector contacts the transition region and is connected to a drain power supply when the source and drain are doped with N-type dopants. On the other hand, the power supply is a source power supply when the source and drain are doped with P-type dopants.

Abstract: The present invention provides a method of and system for reducing the absorption of light by opaque material in a photomask. The method includes providing a photomask substrate, and applying an opaque material to one side of the photomask substrate. The interface between the opaque material and photomask substrate reflects at least 80 percent of the light through the photomask.

Abstract: A floating gate memory device has a floating gate and an insulating layer on the floating gate. A control gate is on the insulating layer. The insulating layer is made up of a molecular matrix with ionic complexes distributed in the molecular matrix. By the application of an electric field, the ionic complexes are dissociable in the molecular matrix to change the resistivity (or conductivity) of the insulating layer. By switching between a high resistivity (low conductivity) state, where charge is retained by the floating gate, to a low resistivity (high conductivity) state, the charge stored on the floating gate can readily drained off to the gate electrode.