Abstract: In a method of forming damascene metallization lines on a substrate by electroplating and chemical mechanical polishing, the metal layer thickness profile is shaped in correspondence to the removal rate during the chemical mechanical polishing. Thus, any non-uniformity of the chemical mechanical polishing process may be compensated for by appropriately depositing the metal layer so that erosion and dishing of the finally obtained metal lines are within tightly selected manufacturing tolerances.

Abstract: A method is provided for manufacturing, the method comprising processing a workpiece, measuring a parameter characteristic of the processing, and forming an output signal corresponding to the characteristic parameter measured by using the characteristic parameter measured as an input to a transistor model. The method also comprises predicting a wafer electrical test (WET) resulting value based on the output signal, detecting faulty processing based on the predicted WET resulting value, and correcting the faulty processing.

Abstract: The present invention relates to a MOS transistor structure and method of manufacture which provides a high-k dielectric gate insulator for reduced gate current leakage while concurrently reducing remote scattering, thereby improving transistor carrier mobility.

Abstract: Analysis of a semiconductor die having silicon-on-insulator (SOI) structure is enhanced by operating a die and detecting a response that is used to analyze selected characteristics of the die. According to an example embodiment of the present invention, a die having a thinned backside is provided for analysis. The die is operated so that one or more portions of circuitry in the die are near a state-changing transition between a failed mode and a recovered mode. An electron-beam probe is directed to the thinned backside, and the probe electrically couples a capacitance load to underlying circuitry via the insulator of the SOI structure. The capacitance load alters the timing margin of a portion of the circuitry and, thereby, causes the circuitry to undergo a state-changing transition. A response from the circuitry related to the transition is detected and used to analyze the die. In this manner, portions of the die being affected by altered timing margins can be detected.

Abstract: A method is provided for selecting a group of memory blocks in a flash memory device given their starting and ending addresses. The method compares the two addresses to determine the multi-block first bit location which is the most significant bit location where the starting and ending addresses have different bits. The method then generates a converted memory block address where bits more significant than the multi-block first bit location are the ending address bits and where bits less significant than, or equal in significance to, the multi-block first bit location are equal to a logic 1. The method also generates a converted complementary memory block address identical to the other converted address except that bits in the bit locations more significant than the multi-block first bit location are the complements of the ending address bits.

Abstract: The present invention provides for a method and an apparatus for using an integrated remote identifier for processing semiconductor wafers. Process data is associated with a remote identifier. A remote identifier interfacing process based upon the remote identifier is performed. A first processing run of semiconductor devices is performed in response to the remote identifier interfacing process.

Abstract: The remotely accessible Integrated Debug Environment of this invention permits a user having only a computer and an Internet connection to remotely access an IDE configured for operating and debugging a selected target microprocessor or microcontroller. An IDE is set up, including a host computer which operates as a web server and as a target/debug controller. One or more target processors may be connected to the host computer, along with debug equipment, such as logic analyzers, ICE equipment, overlay memory, etc. The host computer includes toolsets that correspond to the available target processor(s). In order to execute or debug code on a selected target processor, a user connects to the host computer using a web browser, with which the user can determine the availability of target processors and other pertinent information.

Abstract: A method and apparatus for locating integrated circuit defects associated with different aspects of the integrated circuit industry. The integrated circuit is configured in a known failing mode, with a first power supply providing a constant voltage and variable current. Next, one or more additional dedicated power supplies are connected to various points of interest throughout the integrated circuit, wherein these dedicated power supplies have a preset current and the voltage is allowed to vary. The integrated circuit is then scanned with a laser beam, which induces current changes on in the integrated circuit especially in defective areas. These current changes then cause voltage changes on the dedicated power supplies. When such a voltage change occurs on the dedicated power supplies, its position is noted.

Abstract: A method of determining the composition of a film stack using optical properties is disclosed herein. In one embodiment, the method comprises providing a library of optical characteristic traces, each of which correspond to a film stack combination comprised of multiple process layers, providing a wafer having a film stack formed thereabove, and illuminating the film stack. The method further comprises measuring light reflected off the film stack to generate an optical characteristic trace for the film stack, and determining the composition of the film stack formed above the wafer by correlating or matching the generated optical characteristic trace for the film stack above the wafer to an optical characteristic trace from the library, the optical characteristic trace from the library having an associated film stack composition comprised of a plurality of known process layers.

Abstract: A novel method of operating a physical layer device in a local area network, such as one conforming to Ethernet protocol, to make a single physical layer device compatible with Physical Media Dependent (PMD) devices operating over different network media types. The methodology involves monitoring signal detect inputs and based on their levels, automatically reconfiguring the physical layer device to support interface to a required PMD device. In a preferred embodiment, a physical layer device in a network transceiver for interconnecting a hub device and PMD devices has first transmitting and receiving paths for supporting interface to a first PMD device, such as 100 BASE-TX, and second transmitting and receiving paths for supporting interface to a second PMD device, such as 100 BASE-FX.

Abstract: A method and system for qualifying an oxide-nitride-oxide (QNO) layer including a first oxide layer, a nitride layer and a control oxide layer in a semiconductor device is disclosed. The method and system including determining a first plurality of dielectric breakdown voltages and a first plurality of lifetimes and determining a second plurality of dielectric voltages and a second plurality of lifetimes. The first plurality of dielectric breakdown voltages and lifetimes being determined utilizing a plurality of ramp rates for a first plurality of ONO layers having a particular nitride layer thickness and a plurality of control oxide layer thicknesses. The second plurality of dielectric breakdown voltages and lifetimes layer being determined utilizing the plurality of ramp rates for each of a second plurality of ONO layers having a particular control oxide layer thickness and a plurality of nitride layer thicknesses.

Abstract: A method of manufacturing a semiconductor device by attaching a flip chip die to an organic substrate using solder comprises applying no-clean flux to the flip chip die or the organic substrate; heating the flip chip die and the organic substrate to bond the flip chip die to the organic substrate, and cooling the flip chip die and the organic substrate. The step of heating the flux includes controlling oxygen and moisture content of an atmosphere surrounding the flux, preheating to a temperature of about 145° C. to about 165° C., soaking at a temperature of about 145° C. to about 165° C. for about four to about six minutes, and reflowing above the solder's melting point.

Abstract: A manufacturing method for a MirrorBit® Flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric material. First and second bitlines are implanted and a wordline material is deposited. A hard mask material is deposited over the wordline material. The hard mask material is of a material having the characteristic of being deposited rather than grown. A photoresist material is deposited over the wordline material and is patterned to form a patterned hard mask. The patterned photoresist material is removed. The wordline material is processed using the patterned hard mask to form a wordline. The patterned hard mask material is removed.

Abstract: An apparatus and method are disclosed for maintaining free buffer information for a network switch. A first Random Access Memory (RAM), located on the network switch, functions to store values that indicate whether or not free buffers, located in a second RAM, are available for storing received data frames. An input logic is provided for placing values in the first RAM to indicate which free buffers are available for storing the data frames. When free buffers are required to store data frames, the output logic searches the first RAM and locates values that indicate available free buffers in the second RAM. The output logic then generates buffer pointers that address the locations of the free buffers in the second RAM. The buffer pointers that are generated are stored in a small capacity queue on the network switch to provide immediate availability to free buffers.

Abstract: A computer system that includes a first integrated circuit that has a plurality of first functions. The first integrated circuit is coupled to a second integrated circuit having a plurality of second functions via a communication link that includes a plurality of pipes carrying transactions on the link. Each pipe has a source end in one of the first and second integrated circuits and a target end in the other of the first and second integrated circuits. Each of the pipes is identified by a pipe identifier that uniquely identifies both the source end and the target end of a respective pipe. Each transaction on the link includes a pipe identification field containing the pipe identifier to associate each of the transactions with one of the pipes. The pipes share the link on a packet multiplexed basis. Each pipe can carry either isochronous or asynchronous transactions.

Abstract: A method (M) of determining the effectiveness of a deposited thin conformal barrier layer (30) by forming a test specimen and measuring the copper (Cu) penetration from a metallization layer (40) through the barrier layer (30) (e.g., refractory metals, their nitrides, their carbides, or their other compounds), through a thin insulating dielectric layer (20) (e.g., SiO2), and into a semiconductor (10) substrate (e.g., Si), wherein the interaction between the migrating metal ions and the semiconductor ions are detected/monitored, and wherein the detection/monitoring comprises (1) stripping at least a portion of the insulating dielectric layer (20) and the barrier layer (30) and (2) examining the semiconductor substrate (10) surface of the test specimen, thereby improving interconnect reliability, enhancing electromigration resistance, improving corrosion resistance, reducing copper diffusion, and a test specimen device thereby formed.

Abstract: A floating gate flash memory device including a substrate comprising a source region, a drain region, and a channel region positioned therebetween; a floating gate electrode positioned above the channel region and separated from the channel region by a tunnel dielectric material layer; and a control gate electrode positioned above the floating gate electrode and separated from the floating gate electrode by an interpoly dielectric layer, the interpoly dielectric layer comprising a modified ONO structure having a bottom dielectric material layer adjacent to the floating gate electrode, a top dielectric material layer adjacent to the control gate electrode, and a center layer comprising a nitride and positioned between the bottom dielectric material layer and the top dielectric material layer, in which the tunnel dielectric material layer, and at least one of the bottom dielectric material layer and the top dielectric material layer, comprise a high-K dielectric material.

Abstract: The present invention provides a system and process for controlling the application of patterned resist coatings in an integrated circuit manufacturing process that employs multiple reticle patterns. One aspect of the invention relates to obtaining scatterometry measurements from a patterned resist and using the measurements to determine whether the correct reticle pattern was employed in forming the patterned resist. According to another aspect of the invention, the reticles are provided with grating patterns in addition to reticle patterns, whereby when the reticles are printed, gratings are formed in the resist. The gratings can be used, with scatterometry, to identify the reticle pattern. The reticles can be configured so that the gratings form in a non-functional portion of a wafer, such as a portion along a score line. Where it is, determined that the correct reticle pattern was not used, corrective action can be taken such as stripping the resist and reprocessing the affected wafers.

Abstract: A method is provided, the method including forming a gate dielectric above a surface of the substrate, forming the conductive gate structure above the gate dielectric, the conductive gate structure having an edge region, and forming a source/drain extension (SDE) adjacent the conductive gate structure. The method also includes forming a dopant-depleted-SDE region in the substrate under the edge region of the conductive gate structure.

Abstract: In one illustrative embodiment, the method comprises providing a substrate having a process layer formed thereabove, performing a wet etching process comprised of a duration parameter on the process layer to reduce a thickness of the process layer, and adjusting the duration parameter of the wet etching process if the reduced thickness of the process layer after the etching process is complete is not within acceptable limits. In another illustrative embodiment, the present invention is directed to a system that is comprised of an etch tool for performing an etching process for a duration on a process layer formed above a semiconducting substrate to reduce a thickness of the process layer, and a controller for adjusting the duration of the etching process if the reduced thickness of the process layer after the etching process is performed is not within acceptable limits.