Abstract: The maximum performance state available to a processor in a computer system, in terms of operating frequency and/or voltage, changes according to thermal criteria. When the temperature increases above a predetermined threshold, the maximum performance state available is reduced. Multiple temperature thresholds may be utilized providing for a gradually reduced maximum performance state as temperature increases. When the temperature returns to a lower level, the maximum performance state available is increased. Changing the maximum available performance state according to temperature provides for more gradual reduction in performance as temperature increases, which results in higher average system performance as temperature increases. Thus, a more gradual reduction in performance is provided while still maintaining a high speed rating of the processor in more ideal conditions.

Abstract: A method of compensating for across-wafer variations in photoresist thickness is provided. The method comprises providing a wafer having a process layer formed there-above, forming a layer of photoresist above the process layer, measuring a thickness of the layer of photoresist at a plurality of locations to result in a plurality of thickness measurements, providing the thickness measurements to a controller that determines, based upon the thickness measurements, an exposure dose of an exposure process to be performed on the layer of photoresist, and performing the exposure process on the layer of photoresist using the determined exposure dose. This exposure dose may be varied on a flash-by-flash basis as the stepper tool “steps” across the surface of wafers. That is, the exposure dose for a group of flashes, or for each flash, may be varied in response to the thickness measurements.

Abstract: The present invention is directed to an integrated circuit having an optimized gate coupling capacitance. The integrated circuit includes a substrate defining a trench therein. A first conductive layer has a portion which extends into the trench. The first conductive layer defines a channel fabricated by a blanket etching step. An insulative layer is adjacent the first conductive layer. A second conductive layer is adjacent the insulative layer. The present invention is further directed to a method of fabricating an integrated circuit. The method includes forming a trench in the substrate, filling the trench with a trench fill material, etching the trench fill material until an upper surface of the trench fill material is below an upper surface of the substrate, providing a first conductive layer over at least a portion of the trench fill material, and blanket etching the first conductive layer until the portion is exposed.

Abstract: A network switch configured for switching data packets across multiple ports uses an external memory to store data frames. When a data frame is transmitted to the external memory, a frame header portion of the data frame is stored on the switch for processing by decision making logic. The switch memory is configured to store a number of the frame headers corresponding to each port on the switch along with frame pointer information indicating the location in the external memory where the data frame is stored.

Abstract: The present invention details a method which characterizes an STI fabrication process, and more particularly provides information relating to a variation in the STI sidewall profile between trenches in a middle portion of an array and a trench on an outer portion thereof. The method comprises forming two STI arrays with an STI fabrication process, forming a conductive layer over each array, biasing each conductive layer and determining a current associated therewith. The two current are then utilized to ascertain the variation of interest.

Abstract: An apparatus for programming selected entries in an address filter table allows dynamic updating of address registers and eliminates the need to disable unmodified registers in arrangements including multiple registers or entries. The apparatus comprises an interface for receiving data frames from a remote station. A media access controller is provided with an address filter table capable of storing a plurality of entries. Each entry includes an address field for storing a predetermined target address, and an enable field for indicating whether or not the entry is valid. The media access controller is configured to receive each of the data frames from the interface. The media access controller examines the enable field of each entry in the address filter table to determine whether or not the entry is valid. The received data frames are then routed to a destination address based upon the target addresses stored in the address filter table.

Abstract: Reliable contacts/vias are formed by sputter etching to flare exposed edges of an opening formed in a dielectric layer, depositing a composite barrier layer and then filling the opening with tungsten at a low deposition rate. The resulting contact/via exhibits significantly reduced porosity and contact resistance. Embodiments include sputter etching to incline the edges of an opening formed in an oxide dielectric layer, e.g., a silicon oxide derived from TEOS or BPSG, at an angle of about 83° to about 86°, depositing a thin layer of Ti, e.g., at a thickness of about 250 Å to about 350 Å, depositing at least one layer of titanium nitride, e.g., three layers of titanium nitride, at a total thickness of about 130 Å to about 170 Å, and then depositing tungsten at a deposition rate of about 1,900 to about 2,300 Å/min to fill the opening.

Abstract: Degradation of fluorine-doped silica glass low-k inter-layer dielectrics during fabrication is significantly reduced and resolution of submicron features is improved by the formation of dual nature capping/ARC layers on inter-layer dielectric films. The capping/ARC layer is formed in-situ on a fluorine-doped silica glass inter-layer dielectric. The in-situ formation of the capping/ARC layer provides a strongly adhered capping/ARC layer, formed with fewer processing steps than conventional capping and ARC layers.

Abstract: Semiconductor analysis is enhanced using a system and method for improving the heat-dissipation characteristics of a semiconductor die. According to an example embodiment of the present invention, a flip-chip integrated circuit die having circuitry in a circuit side opposite a back side is formed having a back side including a thermal conductivity enhancing material. The thermal conductivity enhancing material improves the heat dissipating characteristics of the die during operation and testing and helps to reduce or prevent overheating. An epitaxial layer of silicon is formed in the back side, and circuitry is constructed in the epitaxial layer. Pre-existing circuitry on the circuit side and the newly formed circuitry in the back side are electrically coupled.

Abstract: An improved manufacturing process and an improved device made by the process are described for forming via interconnects between metal layers in a multilevel metallization structure. This process essentially eliminates exploding vias due to vias extending beyond the edge of metal lines. The strong reaction is caused by the chemical interaction of metal lines beneath vias with reactants and/or reaction products associated with via fill. An insulating cap layer is deposited on the patterned and etched metal layer before depositing the interlevel dielectric layer above it. A two-step via etch process selectively removes portions of the cap layer within vias prior to via fill. The remaining cap layer within the vias covers, and thereby protects, otherwise vulnerable underlying metal from the damaging chemical interaction during via fill. Using this process, metal borders around vias can be reduced or eliminated, thereby increasing circuit packing density.

Abstract: An asymmetric multi-converter power supply including a first converter and a second converter coupled to provide power to an output node. A control circuit is coupled to the second converter and is configured to selectively enable the second converter depending upon a voltage at the output node. The control circuit may be configured to enable the second converter only in response to determining that the voltage at the output node is not within a predetermined range. Alternatively, the first converter is configured to provide power through a first series inductor and the second converter is configured to provide power to the output node through a second series inductor. The second series inductor having a smaller inductance than the first series inductor. Additionally, the second converter may be characterized by a transient response time that is faster than a transient response time of the first converter.

Abstract: An exemplary embodiment of the disclosure relates to a method of integrated circuit fabrication involving phase shifting materials. This method can include providing a layer of chrome; providing a layer of phase shifting material over the layer of chrome; providing open spaces in the layer of chrome and layer of phase shifting material according to a pattern; removing selected open spaces proximate other open spaces; and transferring the pattern of spaces to the integrated circuit wafer. The portion of the pattern removed by the removing step is transferred to the integrated circuit wafer by side lobe printing.

Abstract: Defect analysis of an integrated circuit die is enhanced using a method and system that make possible the detection of defect-related heat generation in the die. According to an example embodiment of the present invention, a semiconductor die having a liquid crystal layer is analyzed by detecting a liquid crystal phase change caused by heating the die. The heating causes a first circuit region and a second circuit region to effect a separate phase change in corresponding areas of the liquid crystal layer. A detector is adapted to use time-lapsed analysis to detect the liquid crystal phase change in the area corresponding to the second circuit region before the corresponding areas cease to be separately detectable.

Abstract: A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and a via extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The first etch stop layer is disposed over the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The via can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the via, and the sidewall diffusion barrier layer is formed from the same material.as the first diffusion barrier layer. The first diffusion barrier layer can be formed from silicon carbide. A method of manufacturing the semiconductor device is also disclosed.

Abstract: The present invention provides a method and apparatus for correction of machine disturbances for run-to-run control of semiconductor device manufacturing processes. At least one external variable is identified. How the external variable impacts a semiconductor device manufacturing process is determined. A determination whether the impact of the external variable causes an appreciable impact on the semiconductor device manufacturing process is made. At least one control parameter of the semiconductor device manufacturing process is adjusted in response to the determination that the impact of the external variable causes an appreciable impact on the semiconductor device manufacturing process.

Abstract: A method of fabricating an ultra narrow gate electrode for an FET and/or a conductive line in an integrated circuit by first forming a mask for the gate electrode and/or conductive line on a semiconductor substrate of minimal width dimension by optical lithography and reducing the width of the mask by laser irradiation with the beam at an angle and the semiconductor substrate rotating at a high rate of speed.

Abstract: A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and a via extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The first etch stop layer is disposed over the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The via can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the via, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. The first etch stop layer can be formed from silicon oxynitride. A method of manufacturing the semiconductor device is also disclosed.

Abstract: A strong interface is formed between an interconnect and an encapsulating layer to prevent the lateral drift of material from the interconnect along the bottom of the encapsulating layer. Diffusion barrier material is deposited on the top surface of the interconnect using a selective deposition process. The diffusion barrier material may be epitaxially grown from the interconnect during the selective deposition of the diffusion barrier material on the top surface of the interconnect to promote adhesion of the diffusion barrier material to the interconnect. An encapsulating layer is deposited on top of the diffusion barrier material. The diffusion barrier material and the encapsulating layer are comprised of a similar chemical element to promote adhesion of the diffusion barrier material to the encapsulating layer. The diffusion barrier material on the top surface of the interconnect prevents lateral drift of material comprising the interconnect along the encapsulating layer.

Abstract: A network switch, configured for performing layer 2 and layer 3 switching in an Ethernet (IEEE 802.3) network without blocking of incoming data packets, includes a network switch port having a port filter configured for evaluating an incoming data packet on an instantaneous basis. The filter is configured for determining the presence of prescribed layer 3 information in a received data packet. The port filter also signals a switch fabric of the network switch to learn the IP-MAC association of the data packet. The port filter determines whether or not the data packet is part of the data traffic between connected subnetworks of the network switch. With the port filter in the above configuration, the network is enabled to perform layer 3 and layer 2 switching for 100 Mbps and gigabit networks without blocking in the network switch.

Abstract: A method for making a semiconductor structure, includes patterning a photoresist layer to form both a zero marks pattern and a well implant mask pattern. The photoresist layer is on a region of a substrate.