Abstract: The present invention relates to a system and method for calibrating a scanning electron microscope (SEM). The method comprises measuring an electrical characteristic of a calibration standard reference sample feature and correlating the electrical measurement with an SEM measurement thereof. The correlation of the electrical and SEM measurements provides a critical dimension (CD) for the reference sample feature which can then be used to correlate SEM measurements of workpiece features. The system provides a reference sample having a measurable feature electrically connected to a probe. The probe provides an electrical measurement of the reference sample feature. The system further comprises a scanning electron microscope (SEM) adapted to provide an optical measurement of the reference sample feature. A processor is provided to correlate the optical and electrical measurements of the reference sample feature, whereby a reference feature CD is obtained.

Abstract: A processor architecture containing multiple closely coupled processors in a form of symmetric multiprocessing system is provided. The special coupling mechanism allows it to speculatively execute multiple threads in parallel very efficiently. Generally, the operating system is responsible for scheduling various threads of execution among the available processors in a multiprocessor system. One problem with parallel multithreading is that the overhead involved in scheduling the threads for execution by the operating system is such that shorter segments of code cannot efficiently take advantage of parallel multithreading. Consequently, potential performance gains from parallel multithreading are not attainable. Additional circuitry is included in a form of symmetrical multiprocessing system which enables the scheduling and speculative execution of multiple threads on multiple processors without the involvement and inherent overhead of the operating system.

Abstract: A method and apparatus in a network switch port for providing queuing of data frames as they are transferred from a switch port to an external memory. Multiple buffers within the external memory used to store a single data frame are linked together by writing a next buffer location in each buffer header. Storing linking information within each buffer eliminates the need for a separate memory for storing all the buffer locations used to store a data frame, thereby reducing the complexity and cost of the network switch port.

Abstract: The present invention relates to illuminating an interior portion of a processing chamber in a semiconductor processing system. A fiber optic light source is operatively associated with the processing chamber to illuminate the interior of the chamber to facilitate viewing the interior of the chamber.

Abstract: Methods and apparatus for inspecting a feature on a wafer surface are provided. In one aspect a method of inspecting a feature on a film surface is provided that includes illuminating the feature with laser radiation and detecting radiation scattered from the feature with a plurality of detectors. Each of the plurality of detectors has a known position. A position of the feature observed by each of the plurality detectors is computed based upon the radiation scattered from the feature. An average position of the positions observed by each of the plurality of detectors is computed. A first value for each of the plurality of detectors is computed that is the scalar product of the known position of a given detector with the difference of the position of the feature observed by that given detector and the average of the positions observed by each of the plurality of detectors.

Abstract: A novel system is provided for automatically generating caution labels for moisture-sensitive semiconductor devices packed in drypack bags. The system has a scanner that scans a lot number or an ID mark representing ID information of a moisture-sensitive device sealed in a drypack bag, and a computing device with a look-up table containing moisture-sensitivity levels assigned to the moisture-sensitive devices. In response to an ID signal produced by the scanner, the computing device searches the look-up table for a moisture-sensitivity level assigned to the packed moisture-sensitive device. The determined moisture-sensitivity level is supplied by the computing device to a label-formatting device for generating a caution label indicating the moisture-sensitivity level. The label-formatting device controls a printer for printing the generated caution label.

Abstract: In invention provides a system for reducing or eliminating side lobes in patterned resist coatings. The system heats the resist briefly to induce the resist to flow. The system allows the resist to flow long enough for the side lobes to level, but not so long as to corrupt the resist pattern. The original resist pattern may be biased to allow for some flow during the side lobe reduction process. The invention is useful in eliminating side lobes that typically result when an attenuated phase shift mask is used to form a patterned resist coating with fine, sharp-edged features.

Abstract: The present invention relates to a system and method for calibrating a scanning electron microscope (SEM). The method comprises measuring an electrical characteristic of a calibration standard reference sample feature via a current induced by an electron beam (e-beam) and correlating the e-beam induced current measurement with an SEM measurement thereof. The correlation of the e-beam induced current and SEM measurements provides a critical dimension (CD) for the reference sample feature which can then be used to correlate SEM measurements of workpiece features. The system provides a reference sample having a measurable feature electrically connected to a probe. The probe provides an electrical measurement of the reference sample feature based on an e-beam induced current. The system further comprises a scanning electron microscope (SEM) adapted to provide an optical measurement of the reference sample feature and workpiece features.

Abstract: An apparatus and method for detecting a process endpoint. The method includes receiving a first data signal and a second data signal and combining the first data signal and the second data signal to generate a combined data signal. The method also includes detecting a peak in the combined data signal, wherein the peak indicates the process endpoint. The apparatus includes a data collection unit capable of receiving a plurality of data signals and a signal analysis unit. The signal analysis unit is capable of combining the plurality of data signals received through the data collection unit to generate a combined data signal and identifying a peak in the combined data signal indicative of the process endpoint.

Abstract: The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual polysilicon floating gates with an isolation opening between floating gates. Processes for making the memory device according to the invention are also disclosed.

Abstract: Methods are described for fabricating semiconductor devices, in which a tensile film is formed over PMOS transistors to cause a compressive stress therein and a compressive film is formed over NMOS transistors to achieve a tensile stress therein, by which improved carrier mobility is facilitated in both PMOS and NMOS devices.

Abstract: A network switching system configured for evaluating an incoming data packet including layer 3 information having an Internet Protocol (IP) header and an IP checksum. The system includes a buffer memory and network switch. The network switch includes a media access control (MAC) module having a receive data portion and a transmit data portion. The receive data portion is configured to extract the IP checksum from the IP header and to validate the IP checksum. A queue block is configured to send the IP checksum to the buffer memory for storage therein. A layer 3 internal rules checker is configured to receive layer 3 information and to modify the IP header based on a field of the IP header. The internal rules checker generates an identifier indicating the field needs to be changed.

Abstract: A processor supports a processing mode in which the default address size is greater than 32 bits and the default operand size is 32 bits. The default address size may be nominally indicated as 64 bits, although various embodiments of the processor may implement any address size which exceeds 32 bits, up to and including 64 bits, in the processing mode. The processing mode may be established by placing an enable indication in a control register into an enabled state and by setting a first operating mode indication and a second operating mode indication in a segment descriptor to predefined states. Additionally, an instruction prefix may be coded into an instruction to override the default address and/or operand size. Thus, an address size of 32 bits may be used when desired, and an operand size of 64 bits may be used when desired.

Abstract: The present invention is directed to a method of forming halo implants in a semiconductor device. In one illustrative embodiment, the method comprises forming a structure above a semiconducting substrate, forming a layer of photoresist above the structure and the substrate, and positioning the substrate in an exposure tool that has a light source and a focal plane. The method further comprises positioning the surface of the layer of photoresist in an exposure plane that is different from the focal plane of the exposure tool, exposing the photoresist to the light source of the exposure tool while the surface of the photoresist is in the exposure plane, and developing the layer of photoresist to define an opening in the layer of photoresist around the structure on the substrate.

Abstract: A processor is described which includes a stride detect table. The stride detect table includes one or more entries, each entry used to track a potential stride pattern. Additionally, each entry includes a confidence counter. The confidence counter may be incremented each time another address in the pattern is detected, and thus may be indicative of the strength of the pattern (e.g., the likelihood of the pattern repeating). At a first threshold of the confidence counter, prefetching of the next address in the pattern (the most recent address plus the stride) may be initiated. At a second, greater threshold, a more aggressive prefetching may be initiated (e.g. the most recent address plus twice the stride). In some implementations, the prefetch mechanism including the stride detect table may replace a prefetch buffer and prefetch logic in the memory controller.

Abstract: A method and an apparatus for measuring insulating film thickness, such as the width of sidewall spacers. The method includes positioning a first test structure having a first resistance at a first location on a semiconductor wafer and positioning a second test structure having a second resistance different from the first resistance at a second location on the semiconductor wafer. The method also includes measuring the first resistance of the first test structure and measuring the second resistance of the second test structure. The method also includes determining an average characteristic of the first test structure and the second test structure, other than resistance, based on the first resistance of the first test structure and the second resistance of the second test structure.

Abstract: The invention relates to a flash memory devices and a method associated therewith in which combined source/drain regions are shared by more than two memory cells. For example, source/drain regions can be shared by four adjacent memory cells. Such sharing can be accomplished by providing memory cells along main branches of word lines and additional memory cells along dead end branches extending off the main branches. Another aspect of the invention relates to a flash memory device wherein the memory cells are arrayed and a first portion of the memory cells are read with source and drain regions sharing a row of the array and a second portion of the memory cells are read with source and drain regions sharing a column of the array.

Abstract: A method and apparatus for combined transaction reordering and buffer management. The apparatus may include a buffer, a first generator circuit and a second generator circuit. The buffer is configured to store memory transaction responses received from a memory controller in a plurality of addressable locations. The first generator circuit is configured to generate a first memory transaction request encoded with a first tag corresponding to an address in the buffer in response to receiving a first memory request. The second generator circuit is configured to generate a second tag using the size of said first memory request added to the first tag. The first generator circuit may be further configured to generate a second memory transaction request encoded with the second tag corresponding to a second address in the buffer in response to receiving a second memory request successive to the first memory request.

Abstract: A method for removing discoloration and corrosion of an exposed copper surface and for forming a nitride capping layer on top of the surface provides an in-situ process in which the reactive plasma ambient is constantly maintained during a transition from the surface treatment step to the deposition step for forming the nitride capping layer. Permanently maintained plasma avoids an renewed formation of discoloration on the cleaned copper surface during the transition to the deposition step and at the beginning of the deposition step when silane gas is introduced into the plasma ambient. Moreover, the overall process time is significantly reduced.

Abstract: A multiple purpose bus for a flash memory device that allows six sets of data signals to utilize the bus. The multiple purpose bus includes sixteen circuit lines that extend from one end of the memory device to another end of the memory device. Control signals that correspond to each set of data signals couple the sets of data signals to the circuit lines. A grounding circuit is provided that couples the circuit lines to a ground when none of the sets of data signals are utilizing the multiple purpose bus.