Abstract: A method of isolation of active regions on a silicon-on-insulator semiconductor device, including the steps of:
providing a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric isolation layer and a silicon substrate, in which the silicon active layer is formed on the dielectric isolation layer and the dielectric isolation layer is formed on the silicon substrate; etching through the silicon active layer to form an isolation trench, the isolation trench defining an active region in the silicon active layer; forming a liner oxide by oxidation of exposed silicon in the isolation trench; and filling the isolation trench with a tensile stress-reducing low density trench isolation material, without thereafter densifying the tensile stress-reducing low density trench isolation material.
Abstract: Semiconductor devices with improved transistor performance are fabricated by ion-implanting a dopant into the oxide liner to prevent or substantially reduce dopant out-diffusion from the shallow source/drain extensions. Embodiments include ion implanting a P-type dopant, such as B or BF2, using the gate electrode as a mask, to form shallow source/drain extensions, depositing a conformal oxide liner, and ion implanting the P-type impurity into the oxide liner at substantially the same dopant concentration as in the shallow source/drain extensions. Subsequent processing includes depositing a spacer layer, etching to form sidewall spacers, ion implanting to form deep moderate or heavy source/drain implants and activation annealing.
Type:
Grant
Filed:
March 26, 2002
Date of Patent:
June 24, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Andy C. Wei, Mark B. Fuselier, Ping-Chin Yeh
Abstract: A method is provided for determining an etch endpoint. The method includes collecting intensity data representative of optical emission spectral wavelengths during a plasma etch process. The method further includes calculating Scores from at least a portion of the collected intensity data using at most first, second, third and fourth Principal Components derived from a model. The method also includes determining the etch endpoint using Scores corresponding to at least one of the first, second, third and fourth Principal Components as an indicator for the etch endpoint.
Abstract: The present invention relates to a method of forming a stacked gate flash memory cell and comprises forming a tunnel oxide layer, a first conductive layer, an interpoly dielectric layer, and a second conductive layer in succession over a semiconductor substrate. The method further comprises forming a sacrificial layer over the second conductive layer, and patterning the sacrificial layer to form a sacrificial layer feature having at least one lateral sidewall edge associated therewith. A sidewall spacer is then formed against the lateral sidewall edge of the sacrificial layer, wherein the spacer has a width associated therewith, and the patterned sacrificial layer feature is removed. Finally, the second conductive layer, the interpoly dielectric and the first conductive layer are patterned using the spacer as a hard mask, and defining the stacked gate, wherein a width of the stacked gate is a function of the spacer width.
Type:
Grant
Filed:
June 24, 2002
Date of Patent:
June 24, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Angela T. Hui, Kelwin Ko, Hiroyuki Kinoshita, Sameer Haddad, Yu Sun
Abstract: The present invention provides systems and methods wherein scatterometry is used to control an implant processes, such as an angled implant process. According to the invention, data relating to resist dimensions is obtained by scatterometry prior to an the implant process. The data is used to determine whether a resist is suitable for an implant process and/or determine an appropriate condition, such as an angle of implant or implantation dose, for an implant process.
Abstract: In a method of manufacturing a semiconductor device, there are comprised the steps of forming an oxidation preventing layer on a surface of a semiconductor substrate, forming a first window in the oxidation preventing layer, placing the semiconductor substrate in a first atmosphere in which an oxygen gas and a first amount of a chlorine gas are supplied through and then heating the semiconductor substrate at a first temperature such that a first selective oxide film is to grown by thermally oxidizing the surface of the semiconductor substrate exposed from the first window, forming a second window by patterning the oxidation preventing layer, and placing the semiconductor substrate in a second atmosphere in which the oxygen gas and a second amount, which is larger than the first amount, of the chlorine gas are supplied through and then heating the semiconductor substrate at a second temperature such that a second selective oxide film is formed and that a thickness of the first selective oxide film formed below
Abstract: The present invention makes use of ion bombardment to amorphize the source and drain regions of a short channel FET prior to implanting. The source/drain implants are then localized to a shallow depth by appropriate choice of implanting conditions, typically employing rather low bombardment voltages of approximately 10 KeV. Amorphous source/drain regions substantially hinder the diffusion of source/drain dopants and thereby reduce the possibility of punchthrough and loss of FET function. Such devices are preferably used in NAND type flash memory devices maintaining proper self-boosting voltages and FET functions even when short channel lengths are employed.
Type:
Grant
Filed:
August 10, 1999
Date of Patent:
June 17, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Yue-Song He, Kent Kuohua Chang, Allen U. Huang
Abstract: The present invention relates to a system and method of modifying mask layout data to improve the fidelity of mask manufacture. The system and method include determining the difference between the mask layout design and the mask features as written, and generating sizing corrections. The sizing corrections can be used to modify the mask layout data, and/or stored in a database.
Type:
Grant
Filed:
June 20, 2002
Date of Patent:
June 17, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Ramkumar Subramanian, Khoi A. Phan, Bhanwar Singh, Bharath Rangarajan
Abstract: A semiconductor flash memory device is formed with shallow trench isolation (STI) and a low-resistance source bus line (Vss Bus). Embodiments include forming core and peripheral field oxide regions, as by conventional STI techniques, bit lines by ion implantation, polysilicon floating gates above the channel regions and polysilicon word lines. The Vss Bus is then formed by etching away portions of the field oxide between corresponding source regions of adjacent bit lines to expose portions of the substrate, ion implanting impurities into the source regions and the exposed substrate, forming insulating spacers on the sides of the floating gates and word lines, and forming a metal silicide layer, such as titanium silicide, on the implanted source regions and exposed portions of the substrate to form a continuous conductor between the source regions.
Abstract: An embodiment disclosed relates to a variable threshold method of accurately determining a critical dimension (CD) of an integrated circuit feature. This method can include applying a scanning electron microscope (SEM) to an aperture in a layer of material in a portion of an integrated circuit, obtaining a first measurement of a critical dimension of the aperture, applying the SEM again to the aperture, obtaining a second measurement of the critical dimension of the aperture; and determining a depth of focus margin using the first measurement and the second measurement.
Abstract: A command filter selectively forwards received commands to a command queue for in-order execution. If the received command is a probe response command or if probe response information is extracted.from other commands, the probe response is stored in a storage location other than the command queue and executed out-of-order. Data movements specified by memory modifying commands already in the command queue and affecting the cache line in question are also performed out-of-order and the memory modifying command is discarded when it is removed in-order from the command queue.
Type:
Grant
Filed:
June 2, 2000
Date of Patent:
June 17, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Sanjiv K. Lakhanpal, Jennifer Pencis, Chandrakant Pandya, Mark D. Nicol
Abstract: A silicon on insulator (SOI) semiconductor device is provided having a semiconductor substrate with an inverted region, an insulator, and a silicon island. The device combines the inverted region with channel doping to fully deplete the silicon island of majority carriers when the device is in the off state and both of its junctions are at ground.
Abstract: A method and apparatus for automatically verifying whether a network interface is receiving frame data properly. A network interface and a received data checker receive frame data from a network media such as a network or a network model. The network interface processes and transmits the frame data to host memory for storage. The host memory stores the frame data and transmits the frame data to the receive data checker. The receive frame checker compares the frame data from the host memory with the frame data from the network media and generates an indicator signal. The indicator signal indicates whether the network interface is receiving frame data properly. The indicator signal is sent to a display which displays the result.
Abstract: The invention provides a method of small geometry gate formation on the surface of a high-k gate dielectric wherein process complexity and processing costs are reduced while throughput and overall process efficiency is improved. The method may utilize photolithography illumination of 157 nm, 193 nm, 248 nm, or other suitable wavelengths to mask a gate region. An aggressive mask trim may be used to reduce the mask size such that it masks a narrow gate region. A hard mask is then fabricated over the narrow gate region and the gate and high-k dielectric are etched to expose the silicon substrate. The entire etch sequence can be performed in-situ within a single gate etch chamber.
Abstract: A network interface device and a method of transferring data between a host and a network medium employs transmit descriptors that do not contain transmit status information. Upon fetching a transmit data frame from a host system memory at a location pointed to by a transmit descriptor, the network interface device immediately generates an interrupt to the CPU to allow the CPU to re-use the buffers in which the data frame was stored. At the same time, the network interface device attempts transmissions of the data frame to the network medium. Transmit status information is kept in statistics counters on the network interface device.
Abstract: A method of manufacturing a semiconductor device that eliminates the n+ contact implant by using double diffused implants under the core cell contacts by forming core, n-channel and p-channel transistors in a semiconductor substrate, simultaneously forming source and drain DDI implants for the core transistors, forming source and drain Mdd implants for the core transistors, forming source and drain Pldd implants for the p-channel transistors, forming source and drain Nldd implants for the n-channel transistors, forming sidewall spacers on the core, n-channel and p-channel transistors, forming N+ implants for the n-channel transistors, forming P+ implants for the p-channel transistors and forming P+ contact implants for the p-channel transistors.
Abstract: Various methods of fabricating substrate trenches and isolation structures therein are disclosed. In one aspect, a method of fabricating a trench in a substrate is provided. An oxide/nitride stack is formed on the substrate. An opening with opposing sidewalls is plasma etched in the silicon nitride film until a first portion of the oxide film is exposed while second and third portions of the oxide film positioned on opposite sides of the first portion remain covered by first and second portions of the silicon nitride film that project inwardly from the opposing sidewalls. The oxide film is etched for a selected time period in order to expose a portion of the substrate and to define first and second oxide/nitride ledges that project inwardly from the opposing sidewalls. The substrate is etched to form the trench with the first and second oxide/nitride ledges protecting underlying portions of the substrate.
Type:
Grant
Filed:
November 30, 2001
Date of Patent:
June 17, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Srikanteswara Dakshina-Murthy, Christoph Schwan, Jeffrey C. Haines
Abstract: The present invention is directed to a transistor having an enhanced width dimension and a method of making same. In one illustrative embodiment, the transistor comprises a semiconducting substrate, a recessed isolation structure formed in the substrate, the isolation structure defining a recess thereabove, a gate electrode and a gate insulation layer positioned above the substrate, a portion of the gate electrode and the gate insulation layer extending into the recess above the recessed isolation structure, and a source region and a drain region formed in the substrate. In another illustrative embodiment, the transistor comprises a semiconducting substrate, a recessed isolation structure that defines an active area having an upper surface and an exposed sidewall surface, a gate insulation layer and a gate electrode positioned above a portion of the upper surface and a portion of the exposed sidewall surface of the active area, and a source region and a drain region formed in the active area.
Type:
Grant
Filed:
March 20, 2001
Date of Patent:
June 17, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Derick J. Wristers, Jon D. Cheek, John G. Pellerin
Abstract: A method of forming conductive interconnections is disclosed herein. In one illustrative embodiment, the method comprises forming an opening in a layer of insulation material, forming a first plurality of silicon seed atoms in the opening, and performing a first tungsten growing process to form tungsten material in the opening. The method further comprises forming a second plurality of silicon seed atoms in the opening above at least a portion of the tungsten material formed during the first tungsten growing process, and performing at least one additional tungsten growing process after forming the second plurality of silicon seed atoms to further form tungsten material in the opening.
Type:
Grant
Filed:
September 18, 2000
Date of Patent:
June 17, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Clive Martin Jones, Tim Z. Hossain, Amiya R. Ghatak-Roy
Abstract: A digital computer automatically converts an input representation of a pattern of flip-chip integrated circuit interconnect bumps in a format suitable for a circuit design program into an output representation in a format suitable for a package design program. A converter program is adapted by script files to convert the input representation into an intermediate representation in a format suitable for a mechanical design program in which only a layer which includes the bumps is extracted from the input representation which can include a substantial number of layers. A mechanical design program is adapted by scripts to automatically input the intermediate representation, identify and label the interconnects, and create the output representation in which the interconnects are labeled. The mechanical design program can be further adapted by scripts to rotate, mirror and/or shrink the pattern. A package design program inputs the output representation and draws the labeled interconnects.