Patents Assigned to Advanced Micro Devices
  • Patent number: 8374016
    Abstract: An apparatus includes a bit cell of a programmable memory circuit. The bit cell includes a programmable device. The bit cell includes a first device having a first type. The first device is configured to conduct a first current between a first node and a second node in response to a first value of a signal on the word line and a signal on a bit line. The programmable device is configured to be programmed in response to a first level of the first current. The bit cell includes a circuit coupled to the second node. The circuit is configured to reduce a leakage current through the first device in response to a second value of the signal on the word line and based on a feedback signal. In at least one embodiment of the apparatus, the feedback signal is based on a signal on the bit line.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: February 12, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Jeffrey A. Correll
  • Patent number: 8374039
    Abstract: A multi-port memory array is disclosed. The memory array includes a plurality of memory subblocks and an output network. Each memory subblock includes a plurality of single-read-port memory cells. The output network is configured to redirect information read for a first read port to a second read port on a condition that an equivalence signal indicates that read addresses for the first read port and the second read port are the same. The latching and multiplexing operation may be integrated. The memory cells may be 6-transistor synchronous random access memory (SRAM) cells, 8-transistor SRAM cells, or any type of memory cells.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: February 12, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David Hugh McIntyre, Jimmy L. Reaves
  • Publication number: 20130034160
    Abstract: Methods and apparatus for facilitating motion estimation in video processing are provided. Preferably, coordinates of a search area within a video frame are determined for each of a plurality of macroblocks (MBs) of a reference frame based upon a predicted location derived from the coordinates of the MB within the reference frame and motion estimation information. The video frame can be segmented into tiles and associated overlapping tile defined for at least some tiles. Search data is defined for each tile as pel data for each pixel within that tile and any associated tile. Macroblock searches are preferably conducted on a tile assignment basis with tile search assignments distributed among a plurality of processing elements. Each processing element preferably has a local memory it uses for the search data when performing a tile search assignment.
    Type: Application
    Filed: August 2, 2011
    Publication date: February 7, 2013
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Michael L. Schmit, John W. Brothers, Radhakrishna Giduthuri
  • Publication number: 20130036295
    Abstract: A system and method for efficient garbage collection. A general-purpose central processing unit (CPU) sends a garbage collection request and a first log to a special processing unit (SPU). The first log includes an address and a data size of each allocated data object stored in a heap in memory corresponding to the CPU. The SPU has a single instruction multiple data (SIMD) parallel architecture and may be a graphics processing unit (GPU). The SPU efficiently performs operations of a garbage collection algorithm due to its architecture on a local representation of the data objects stored in the memory. The SPU records a list of changes it performs to remove dead data objects and compact live data objects. This list is subsequently sent to the CPU, which performs the included operations.
    Type: Application
    Filed: September 24, 2012
    Publication date: February 7, 2013
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Advanced Micro Devices, Inc.
  • Patent number: 8368703
    Abstract: Many computing device may now include two or more graphics subsystems. The multiple graphics subsystems may have different abilities, and may, for example, consume differing amount of electrical power, with one subsystem consuming more average power than the others. The higher power consuming graphics subsystem may be coupled to the device and used instead of, or in addition to, the lower power consuming graphics subsystem, resulting in higher performance or additional capabilities, but increased overall power consumption. By transitioning from the use of the higher power consuming graphics subsystem to the lower power consuming graphics subsystem, while placing the higher power consuming graphics subsystem in a lower power consumption mode, overall power consumption is reduced. A processor executes application software and driver software. The driver software includes first and second driver components for respectively controlling operation of the first and second graphics subsystems.
    Type: Grant
    Filed: December 15, 2008
    Date of Patent: February 5, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Paul Blinzer, Phil Mummah
  • Patent number: 8367493
    Abstract: A method of manufacturing a non-volatile memory device includes forming a number of memory cells. The method also includes depositing a first dielectric layer over the memory cells, where the first dielectric layer is a conformal layer having a substantially uniform thickness. The method further includes depositing a second dielectric layer over the first dielectric layer. Together, the first and second dielectric layers form an interlayer dielectric without voids.
    Type: Grant
    Filed: April 20, 2005
    Date of Patent: February 5, 2013
    Assignees: Spansion LLC, Advanced Micro Devices, Inc.
    Inventors: Minh Van Ngo, Hirokazu Tokuno, Angela T. Hui, Wenmei Li, Hsiao-Han Thio
  • Patent number: 8368221
    Abstract: By forming the first metallization layer of a semiconductor device as a dual damascene structure, the contact elements may be formed on the basis of a significantly reduced aspect ratio, thereby enhancing process robustness and also improving electrical performance of the contact structure.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: February 5, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Frank Feustel, Kai Frohberg, Thomas Werner
  • Patent number: 8370669
    Abstract: A memory device includes memory sleep logic operative to detect a repetitive pattern within at least one memory block, and place the memory block into a sleep mode in response to detecting the repetitive pattern. The memory device memory sleep logic may also provide a response to read commands to the memory block while it is in sleep mode, where the response is a constant output for any address location of the memory block. The memory device memory sleep logic may include pattern detection logic, associated with each memory block, to detect the repetitive pattern; and data port logic, coupled to the pattern detection logic, operative to receive an activation command from the pattern detection logic, and operative to return a constant output pattern in response to any read command to read data from the memory block.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: February 5, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Mikhael Lerman
  • Patent number: 8369133
    Abstract: A method, electronic device, and system are provided in which data is stored in a gateable retention storage element. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus which includes a silicon chip. The method includes storing a data value in a storage element, wherein the storage element is at least one of a flip-flop, a latch or a register. The method also includes placing the storage element in a low power state comprising removing one or more existing connections between the actual ground node and at least one other component in the storage element. The method also includes maintaining the data value in the storage element subsequent to placing the storage element into the low power state. The electronic device includes a storage component for storing a data value.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: February 5, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Aswin K. Gunasekar, Daniel W. Bailey, Aaron S. Rogers
  • Patent number: 8370775
    Abstract: A method for determining a predicted soft error rate (SER) for an integrated circuit device design includes calculating the SER based on a predicted amount of charge imparted by a one or more particles to the integrated circuit device based on the design. The SER is further based on a predicted sensitivity level of a region of the integrated circuit device to the charge imparted by the one or more particles, and can also be based on the energy spectrum of the particles.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: February 5, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Cristian Constantinescu
  • Patent number: 8368219
    Abstract: A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: February 5, 2013
    Assignees: Advanced Micro Devices, Inc., Spansion LLC
    Inventors: Arvind Halliyal, Zoran Krivokapic, Matthew S. Buynoski, Nicholas H. Tripsas, Minh Van Ngo, Mark T. Ramsbey, Jeffrey A. Shields, Jusuke Ogura
  • Patent number: 8361858
    Abstract: The growth rate in a selective epitaxial growth process for depositing a threshold adjusting semiconductor alloy, such as a silicon/germanium alloy, may be enhanced by performing a plasma-assisted etch process prior to performing the selective epitaxial growth process. For example, a mask layer may be patterned on the basis of the plasma-assisted etch process, thereby simultaneously providing superior device topography during the subsequent growth process. Hence, the threshold adjusting material may be deposited with enhanced thickness uniformity, thereby reducing overall threshold variability.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: January 29, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Stephan Kronholz, Andreas Naumann, Gunda Beernink
  • Publication number: 20130021064
    Abstract: A device may include a latch activated during a second phase of a clock cycle; a clock gating component to control when a clock signal is to reach the latch; a destination storage element activated during a first phase of the clock cycle, where a logical path exists from the latch to the destination storage element; and a blocking element located in the logical path from the latch to the destination storage element, where the blocking element includes, as a first input, an output of the latch and, as a second input, an output of the clock gating component, and where the blocking element prevents an output value of the latch from changing when the clock gating component is not enabled and does not prevent the output value of the latch from changing when the clock gating element is enabled.
    Type: Application
    Filed: July 20, 2011
    Publication date: January 24, 2013
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Dwight K. Elvey, Premlatha Paga
  • Patent number: 8357268
    Abstract: By providing an enhanced drive system for electrochemical etch process tools, the operational range, as well as the reliability, may be enhanced. For this purpose, a high torque electric motor may be used in combination with an appropriate power transmission, which may be attached to a corresponding tool frame at a height level that is above a corresponding height level at which respective chemicals are provided to the substrate under process. Hence, the probability for contamination by chemicals may be significantly reduced, thereby also reducing maintenance efforts resulting in reduced production costs.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: January 22, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael Pietzner, Mario Illgen, Kerstin Siury, Frank Kuechenmeister
  • Patent number: 8358158
    Abstract: A method and apparatus for generating a clock that can be switched in phase within a reduced interval of dead time are disclosed.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: January 22, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Brian W. Amick, Ryan J. Hensley, Warren R. Anderson, Joseph E. Kidd
  • Patent number: 8356165
    Abstract: An approach to region selection which extends beyond traces and selects super-regions. A super-region (SR) contains arbitrary control flow, such as interprocedural nested loops, that provides a larger scope for transformation (e.g. optimization) than traces. Hardware samples are used to identify SRs that contain the hot code of a client process without requiring any static program information.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: January 15, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Steven T. Tye, Michael Bedy, Richard L. Ford, Alex Shye
  • Patent number: 8356270
    Abstract: A system and method for providing a statistical budgeting approach to modeling reliability effects such as interconnect electromigration (EM), transistor time-dependant dielectric breakdown (TDDB), hot-carrier injection effects (HCI) and bias temperature instability (BTI) is disclosed. A static analysis flow captures the effects of design topology, switching constraints, interactions between signal nets and supply rails as well as thermal gradients due to interconnect and transistor self as well as mutual heating, and was used to verify successive iterations of deep sub-micron integrated circuit designs.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: January 15, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Tom Burd, Yuri Apanovich, Srinivasaraghavan Krishnamoorthy, Vishak Kumar Venkatraman, Anand Daga
  • Patent number: 8356130
    Abstract: A method includes recording a user-level interrupt as undeliverable in a mailbox at least partially based on an interrupt domain identifier and an interrupt recipient identifier included in a user-level interrupt message associated with the user-level interrupt. The recording is at least partially based on an indication that the user-level interrupt is undeliverable to a recipient application thread executing on a processor core of a plurality of processor cores in a multi-core system.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: January 15, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Karin Strauss, Jaewoong Chung
  • Patent number: 8356155
    Abstract: A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: January 15, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Shawn Searles, Nicholas T. Humphries, Brian W. Amick, Richard W. Reeves, Hanwoo Cho, Ronald L. Pettyjohn
  • Patent number: 8352688
    Abstract: A method and apparatus are disclosed for implementing early release of speculatively read data in a hardware transactional memory system. A processing core comprises a hardware transactional memory system configured to receive an early release indication for a specified word of a group of words in a read set of an active transaction. The early release indication comprises a request to remove the specified word from the read set. In response to the early release request, the processing core removes the group of words from the read set only after determining that no word in the group other than the specified word has been speculatively read during the active transaction.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: January 8, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jaewoong Chung, David S. Christie, Michael P. Hohmuth, Stephan Diestelhorst, Martin T. Pohlack, Luke Yen