Abstract: An integrated circuit (IC) chip having repeaters for propagating signals along relatively long wires that extend between and among lower-level physical blocks of the IC chip, wherein the repeaters are implemented as clocked flip-flops (or “repeater flops”). A method for automatically inserting and allocating such repeater flops during the logical and physical design of the IC chip is also provided.

Abstract: Apparatus and methods for a bilinear filter system comprising a pre-formatter module, a bilinear module, an accumulator module, and a format module. The pre-formatter module is configured to receive texel data and convert it to a normalized fixed point format. The bilinear module is dynamically reconfigurable to perform an interpolation or an extended precision interpolation on the normalized fixed point texel data from the pre-formatter module and generate re-normalized floating point texel data. The interpolator analyzes the exponent range of fixed point texel data from the pre-formatter module to determine if an extended precision calculation is appropriate. The accumulator module is configured to accumulate floating point texel data from the bilinear module to achieve the desired level of bilinear, trilinear, and anisotropic filtering. The format module is configured to convert texel data from the accumulator module into a standard floating point representation.

Abstract: A method includes accepting for a first processor core of a plurality of processor cores in a multi-core system, a user-level interrupt indicated by a user-level interrupt message when an interrupt domain of an application thread executing on the first processor core and a recipient identifier of the application thread executing on the first processor core match corresponding fields in the user-level interrupt message.

Abstract: A video processing apparatus, for use in a video receiver, includes a decoder configured to decode encoded video information into decoded video information and to output the decoded information, and a configuration module coupled to the decoder and configured to a provide a control signal to the decoder indicative of a reduced-image portion of the video frames to be displayed, where the decoder is configured to respond to the control signal by decoding first macroblocks of the video information within the reduced-image portion and second macroblocks of the video information, in a reference section, adjacent the first macroblocks to account for motion of the images in the reduced-image portion without decoding third macroblocks lying outside of the reduced-image portion and the reference section.

Abstract: A system and method are disclosed for providing improved processing of video data. A multi-instance encoding module receives combined video and audio input, which is then separated into a video and audio source streams. The video source stream is pre-processed and corresponding video encoder instances are initiated. The preprocessed video source stream is split into video data components, which are assigned to a corresponding encoder instance. Encoding operations are performed by each video encoder instance to generate video output components. The video output components are then assembled in a predetermined sequence to generate an encoded video output stream. Concurrently, the audio source stream is encoded with an audio encoder to generate an encoded audio output stream. The encoded video and audio output streams are combined to generate a combined encoded output stream, which is provided as combined video and audio output.

Abstract: A system and method for allocating memory to multi-threaded programs on a Non-Uniform Memory Access (NUMA) computer system using a NUMA-aware memory heap manager is disclosed. In embodiments, a NUMA-aware memory heap manager may attempt to maximize the locality of memory allocations in a NUMA system by allocating memory blocks that are near, or on the same node, as the thread that requested the memory allocation. A heap manager may keep track of each memory block's location and satisfy allocation requests by determining an allocation node dependent, at least in part, on its locality to that of the requesting thread. When possible, a heap manger may attempt to allocate memory on the same node as the requesting thread. The heap manager may be non-application-specific, may employ multiple levels of free block caching, and/or may employ various listings that associate given memory blocks with each NUMA node.

Abstract: Embodiments allow a smaller, simpler hardware implementation of an input/output memory management unit (IOMMU) having improved translation behavior that is independent of page table structures and formats. Embodiments also provide device-independent structures and methods of implementation, allowing greater generality of software (fewer specific software versions, in turn reducing development costs).

Abstract: An improved interface technique for use in a southbridge or I/O hub or in similar devices is provided where non-posted read requests are received from at least one requestor, and upstream commands based on these requests are transmitted. Response data is received in reply to commands that were previously transmitted, and responses are transmitted to the at least one requester based on the response data. A buffer unit is provided for storing command identification data that identifies commands that were already transmitted or that are still to be transmitted, and response availability data that specifies response data that has been received by the receive engine. The improvement may enable multiple outstanding read requests.

Abstract: The thickness of drain and source areas may be reduced by a cavity etch used for refilling the cavities with an appropriate semiconductor material, wherein, prior to the epitaxial growth, an implantation process may be performed so as to allow the formation of deep drain and source areas without contributing to unwanted channel doping for a given critical gate height. In other cases, the effective ion blocking length of the gate electrode structure may be enhanced by performing a tilted implantation step for incorporating deep drain and source regions.

Abstract: Based on a driver programmable stencil reference value command, stencil reference value logic produces a plurality of stencil reference values for a corresponding plurality of pixels or pixel samples. At least one of the plurality of stencil reference values has a different value than at least one other of the plurality of stencil reference values. The driver programmable stencil reference value command may include a reference to instruction data or instruction data itself such that the graphics processing logic produces the plurality of stencil reference values based on the instruction data. Stencil logic performs a stencil test on the produced plurality of stencil reference values with respect to or without reference to a previously produced plurality of stencil values. Stencil logic performs stencil operations based on the result of the stencil test.

Abstract: Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.

Abstract: Methods, systems, and computer readable media embodiments are disclosed for preemptive context-switching of processes running on an accelerated processing device. A method includes, responsive to an exception upon access to a memory by a process running on a accelerated processing device, whether to preempt the process based on the exception, and preempting, based upon the determining, the process from running on the accelerated processing device.

Abstract: Methods, systems, and computer readable media for preemptive context-switching of processes on an accelerated processing device are based upon a comparison of the running time of the process and a threshold time quanta. A method includes preempting a process running on an accelerated processing device based upon a running time of the process and a threshold time quanta.

Abstract: A method for synchronizing a receiver to a received signal begins by down-converting the received signal to a first baseband signal. A coarse frequency offset (CFO) of the first baseband signal is determined and is applied to the down-converting of the received signal to a second baseband signal. A fine frequency offset (FFO) of the second baseband signal is determined. The receiver is synchronized to the received signal using the CFO and the FFO.

Abstract: A threshold adjusting semiconductor material, such as a silicon/germanium alloy, may be provided selectively for one type of transistors on the basis of enhanced deposition uniformity. For this purpose, the semiconductor alloy may be deposited on the active regions of any transistors and may subsequently be patterned on the basis of a highly controllable patterning regime. Consequently, threshold variability may be reduced.

Abstract: A method, apparatus, and a system for generating a binary mapping of wafer regions using measured value. A first measured value relating to processing a first workpiece is acquired. A second measured value relating to a second workpiece is acquired. At least a first region common to the first and second workpieces is defined. A determination is made as to whether the results associated with the first or second measured value is above a predetermined threshold. A first binary value is assigned to the first region based upon a determination that the results associated the first or second measured value data is above the threshold.

Abstract: Methods for removing a photoresist from a metal-comprising material are provided. In accordance with an exemplary embodiment of the present invention, the method comprises applying to the photoresist a substantially non-aqueous-based solvent having a pH no less than about 9 or no pH and subsequently applying to the metal-comprising material an aqueous-based fluid having a pH no less than about 9.

Abstract: Embodiments of systems and methods for improved first-in-first-out (FIFO), last-in-last out (LIFO) and full-cycle decoders are described herein. In the various embodiments of the system, a clock generator is operable to generate a clock signal having an active phase and an inactive phase. A set of monotonic flip-flops are operable to capture a set of incoming data addresses during the active cycle of the clock and to generate therefrom data corresponding to single bits in the addresses that have changed compared to the data addresses received by the set of monotonic flip-flops during an immediately preceding data capture cycle. A set of static flip-flops are operable to capture a set of incoming data addresses during the inactive phase of the clock cycle and to generate set output data therefrom. A decoder operable to process the set output data from the set of static flip-flops and to generate a set of old wordlines corresponding to a set of data addresses in the immediately preceding data capture cycle.

Abstract: The gate and active regions of a device are formed and alternating steps of applying and removing nitride and oxide layers allows exposing silicon in different areas while keeping silicon or polysilicon in other area covered with nitride. Metal layers are deposited over the exposed silicon or polysilicon and annealing forms a silicide layer in the selected exposed areas. The oxide and/or nitride layers are removed from the covered areas and another metal layer is deposited. The anneal process is repeated with silicide of one thickness formed over the second exposed areas with additional thickness of silicide formed over the previous silicide thickness.

Abstract: Embodiments of the present invention provide a method of preempting a task. The method includes removing the task from the parallel processors via a scheduling mechanism. Responsive to the removing, the method also includes ceasing (i) retrieval of commands from a buffer associated with the task, (ii) dispatch of groups of work-items associated with the task, (iii) dispatch of wavefronts associated with the task, and (iiii) execution of the wavefronts. State information related to the task is saved.