Abstract: A method of automatic deposition profile targeting for electrochemically depositing copper with a position-dependent controllable plating tool including the steps of depositing copper on a patterned product wafer, measuring an actual thickness profile of the deposited copper and generating respective measurement data, feeding the measurement data to an advanced process control (APC) model and calculating individual corrections for plating parameters in the position-dependent controllable plating tool.

Abstract: A system and method for efficient garbage collection. A general-purpose central processing unit (CPU) partitions an allocated heap according to a generational garbage collection technique. The generations are partitioned into fixed size cards. The CPU marks indications of qualified dirty cards during application execution since the last garbage collection. When the CPU detects a next garbage collection start condition is satisfied, the CPU sends a notification to a special processing unit (SPU) corresponding to a determination of one or more card root addresses, each card root address corresponding to one of said marked indications. The SPU has a single instruction multiple data (SIMD) parallel architecture and may be a graphics processing unit (GPU). The SPU may utilize the parallel architecture of its SIMD core to simultaneously compute multiple card root addresses. Following, the SPU sends these addresses to the CPU to be used in a garbage collection algorithm.

Abstract: A method and apparatus is provided for associating operational data with workpieces and correlating the operational data with yield data. The method comprises processing a workpiece using a processing tool, associating the operational data with the workpiece during the processing of the workpiece and measuring the yield data associated with the processed workpiece. The method further comprises correlating the operational data with the yield data to make one or more determinations.

Abstract: A method and apparatus are described for providing timing information to a view placement interactive (VPI) tool user designing a multi-cell circuit. A circuit design comprising a plurality of cells is displayed to the user. Each cell includes a pre-characterized circuit structure. A graphical user interface (GUI) may be used to request a cell placement change, a design connectivity change or a cell type change. The circuit design is modified to implement the requested change, an incremental static timing analysis is performed, and the resulting timing information associated with the requested change is presented on the displayed circuit design. Timing information may be displayed directly on a cell that receives an output from the particular cell, and/or may be displayed adjacent to the particular cell. The timing information may include current and previous frequency slack information associated with each input and output pin of the particular cell.

Abstract: An apparatus includes a capacitor coupled between a first node responsive to receive an input signal and a second node. The apparatus includes a first circuit coupled to the second node and a third node. The first circuit is selectively operable to separately configure at least one of a low-frequency gain of an equalizer and a pole of the equalizer. The equalizer includes the first circuit and the capacitor. The second node is responsive to receive an equalized version of an AC signal of the input signal in a first mode of the apparatus. The second node is responsive to receive a non-equalized version of the AC signal of the input signal in a second mode of the apparatus. The equalized version of the AC signal of the input signal may be a level-shifted and equalized version of the AC signal in the first mode of the apparatus.

Abstract: A contact element may be formed on the basis of a hard mask, which may be patterned on the basis of a first resist mask and on the basis of a second resist mask, to define an appropriate intersection area which may represent the final design dimensions of the contact element. Consequently, each of the resist masks may be formed on the basis of a photolithography process with less restrictive constraints, since at least one of the lateral dimensions may be selected as a non-critical dimension in each of the two resist masks.

Abstract: A technique for dynamically controlling microprocessor power plane voltage levels includes storing in a memory on a voltage regulator voltage control identifiers in a table accessible according to performance state. In at least one embodiment of the invention, a method includes transitioning a voltage output of a voltage regulator to a next voltage level associated with a next performance state of a processor coupled to the voltage regulator based on a performance state indicator received from the processor and a corresponding entry of a performance state table. In at least one embodiment, the method includes loading performance state table entries into a storage device on the voltage regulator circuit.

Abstract: A memory device and a method of making the memory device are provided. A first dielectric layer is formed on a substrate, a floating gate is formed on the first dielectric layer, a second dielectric layer is formed on the floating gate, a control gate is formed on the second dielectric layer, and at least one film, including a conformal film, is formed over a surface of the memory device.

Abstract: A method of accessing a memory includes accessing multiple ECC words via a single memory channel. Portions of each ECC word are retrieved from different memory ranks, so that a failure in a memory device at one memory rank is less likely to result in uncorrectable errors in the data segment. By accessing the data segments via a single memory channel, rather than multiple memory channels, the single memory channel can be accessed independently, providing for lower cost memory modules, higher memory bandwidth, and lower power dissipation.

Abstract: A conductive cap material for a copper region may be provided with enhanced etch resistivity by taking into consideration the standard electrode potential of one or more of the species contained therein. For example, instead of a conventionally used CoWP alloy, a modified alloy may be used, by substituting the cobalt species by a metallic species having a less negative standard electrode potential, such as nickel. Consequently, device performance may be enhanced, while at the same time the overall process complexity may be reduced.

Abstract: A method, computer program product, and system are provided for controlling a clock distribution network. For example, an embodiment of the method can include programming a predetermined delay time into a plurality of processing elements and controlling an activation and de-activation of these processing elements in a sequence based on the predetermined delay time. The processing elements are located in a system incorporating the clock distribution network, where the predetermined delay time can be programmed in a control register of a clock gate control circuit residing in the processing element. Further, when controlling the activation and de-activation of the processing elements, this activity can be controlled with a state machine based on the system's mode of operation.

Abstract: Embodiments of a dynamic leakage control circuit for use with graphics processor circuitry are described. The dynamic leakage control circuit selectively enables back biasing of the transistors comprising the graphics processor circuits during particular modes of operation. The back biasing levels are controlled by two separate power rails. A first power rail is coupled to an existing power supply and the second power rail is coupled to a separate adjustable voltage regulator. A separate voltage regulator may also be provided for the first power rail. A hardware-based state machine or software process is programmed to detect the occurrence of one or more modes of operation and adjust the voltage regulators for the first and second power rails to either enable or disable the back biasing state of the circuit, or alter the threshold voltage of the circuit within a specified voltage range.

Abstract: Sum and carry signals are formed representing a product of a first and a second operand. A bias signal is formed having a value determined by a sign of a product of the first and the second operand. An output signal is provided based on an addition of the sum signal, the carry signal, a sign-extended addend, and the bias signal. A portion of the output signal, a saturated minimum value, or a saturated maximum value, is selected as a final result based on the sign of the product and a sign of the output signal.

Abstract: An apparatus and methods for scheduling and executing commands issued by a first processor, such as a CPU, on a second processor, such as a GPU, are disclosed. In one embodiment, a method of executing processes on a graphics processing unit (GPU) includes monitoring one or more buffers in a memory, selecting a first subset from the one or more buffers for execution on the GPU based on a workload profile of the GPU, and executing the first subset on the GPU. The GPU may also receive a priority ordering of the one or more buffers, where the selecting is further based on the received priority ordering. By performing prioritization and scheduling of commands in the GPU, system performance is enhanced.

Abstract: A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).

Abstract: A method of fabricating a semiconductor device begins by forming a layer of hard mask material on a substrate comprising a layer of semiconductor material and a layer of insulating material overlying the layer of semiconductor material, such that the layer of hard mask material overlies the layer of insulating material. A multiple exposure photolithography procedure is performed to create a combined pattern of photoresist features overlying the layer of hard mask material, and a recess line pattern is in the hard mask material, using the combined pattern of photoresist features. The method continues by covering designated sections of the recess line pattern with a blocking pattern of photoresist features, and forming a pattern of trenches in the insulating material, where the pattern of trenches is defined by the blocking pattern of photoresist features and the hard mask material.

Abstract: Provided is a method for performing channel estimation in an Orthogonal Frequency Division Multiplexed (OFDM) signal. The method includes performing the channel estimation based upon use of reserved tone channel carriers.

Abstract: In one embodiment, a method comprises in response to an intercept of a first instruction in a guest that is controlled by a virtual machine monitor (VMM), updating first tracking data corresponding to the first instruction in an intercept tracking table; determining, from the first tracking data, that a translation of the first instruction into a first routine is to be performed; and caching the first routine to be executed in response to a subsequent intercept of the first instruction, wherein the first routine is formed from instructions defined in a same instruction set architecture as the first instruction. In some embodiments, a routine for an intercepted instruction that is within a merge window of the first instruction in a guest may be merged into the same routine with the first instruction.

Abstract: A device is provided that includes a structure having a sidewall surface, a layer of material provided on the sidewall surface, and a device structure provided in contact with the layer of material. Fabrication techniques includes a process that includes forming a structure having a sidewall surface, forming a layer of material on the sidewall surface, and forming a device structure in contact with the layer of material, where the device structure and the layer of material are components of a device.

Abstract: Various thermal interface structures and methods are disclosed. In one aspect, a method of manufacturing is provided. The method includes providing plural carbon nanotubes in a thermal interface structure. The thermal interface structure is soldered to a side of a semiconductor chip. In another aspect, an apparatus is provided. The apparatus includes a thermal interface structure that has plural carbon nanotubes. A semiconductor chip is soldered to the thermal interface structure.