Patents Assigned to Advanced Micro Devices
  • Double deposition of a stress-inducing layer in an interlayer dielectric with intermediate stress relaxation in a semiconductor device
    Patent number: 8349744
    Abstract: Enhanced efficiency of a stress relaxation implantation process may be achieved by depositing a first layer of reduced thickness and relaxing the same at certain device regions, thereby obtaining an enhanced amount of substantially relaxed dielectric material in close proximity to the transistor under consideration, wherein a desired high amount of stressed dielectric material may be obtained above other transistors by performing a further deposition process. Hence, the negative effect of the highly stressed dielectric material for specific transistors, for instance in densely packed device regions, may be significantly reduced by depositing the highly stressed dielectric material in two steps with an intermediate relaxation implantation process.
    Type: Grant
    Filed: November 17, 2008
    Date of Patent: January 8, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kai Frohberg, Uwe Griebenow, Katrin Reiche, Heike Berthold
  • Method and system for data prefetching for loops based on linear induction expressions
    Patent number: 8352686
    Abstract: An efficient and effective compiler data prefetching technique is disclosed in which memory accesses may be prefetched are represented in linear induction expressions. Furthermore, indirect memory accesses indexed by other memory accesses of linear induction expressions in scalar loops may be prefetched.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: January 8, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Dz-ching Ju
  • Microstructure device including a metallization structure with self-aligned air gaps and refilled air gap exclusion zones
    Patent number: 8344474
    Abstract: In a sophisticated metallization system, self-aligned air gaps may be provided in a locally selective manner by using a radiation sensitive material for filling recesses or for forming therein the metal regions. Consequently, upon selectively exposing the radiation sensitive material, a selective removal of exposed or non-exposed portions may be accomplished, thereby resulting in a highly efficient overall manufacturing flow.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: January 1, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Robert Seidel, Thomas Werner
  • Method and apparatus for addressing and improving holds in logic networks
    Patent number: 8347250
    Abstract: A method and apparatus for modifying a synchronous logic network so that the hold slack calculated at all pins is greater than or equal to a user-specified threshold, with the condition that the setup slack at any pin does not become negative or smaller than a user-specified margin. The result is an improved design which is less likely to fail due to a hold time violation. The method and apparatus introduce a limited number of logic cells which helps keep power consumption and design size to a minimum.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: January 1, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: George A. Gonzalez, Pete J. Hannan, William A. McGee, Vasant Palisetti, Ashok Venkatachar
  • Filtering method and apparatus for anti-aliasing
    Patent number: 8345063
    Abstract: Embodiments of a filtering method and apparatus for anti-aliasing as described herein take advantage of improved existing hardware by using as input the data stored in the multisampling anti-aliasing (MSAA) buffers after rendering. The standard hardware box-filter is then replaced with a more intelligent resolve implemented using shader programs. Embodiments find scene edges using existing samples generated by Graphics Processing Unit (GPU) hardware. Using samples from a footprint larger than a single pixel, a gradient is calculated matching the direction of an edge. A non-linear filter over contributing samples in the direction of the gradient gives the final result.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: January 1, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Konstantine Iourcha, Jason Yang, Andrew Pomianowski
  • Technique for enhancing dopant profile and channel conductivity by millisecond anneal processes
    Patent number: 8338885
    Abstract: During the fabrication of advanced transistors, significant dopant diffusion may be suppressed by performing a millisecond anneal process after completing the basic transistor configuration, wherein a stress memorization technique may also be obtained by forming a strain-inducing area within a sidewall spacer structure. Due to the corresponding void formation in the spacer structure, a high tensile strain component may be obtained, in the adjacent channel region.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: December 25, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jan Hoentschel, Thomas Feudel, Ralf Illgen
  • Semiconductor chip with reinforcing through-silicon-vias
    Patent number: 8338961
    Abstract: A method of manufacturing includes connecting a first end of a first through-silicon-via to a first die seal proximate a first side of a first semiconductor chip. A second end of the first thu-silicon-via is connected to a second die seal proximate a second side of the first semiconductor chip opposite the first side.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: December 25, 2012
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Michael Z. Su, Gamal Refai-Ahmed, Bryan Black
  • Technique for reducing topography-related irregularities during the patterning of a dielectric material in a contact level of closely spaced transistors
    Patent number: 8338314
    Abstract: In a dual stress liner approach, the surface conditions after the patterning of a first stress-inducing layer may be enhanced by appropriately designing an etch sequence for substantially completely removing an etch stop material, which may be used for the patterning of the second stress-inducing dielectric material, while, in other cases, the etch stop material may be selectively formed after the patterning of the first stress-inducing dielectric material. Hence, the dual stress liner approach may be efficiently applied to semiconductor devices of the 45 nm technology and beyond.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: December 25, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ralf Richter, Heike Salz, Robert Seidel
  • Fluorine-passivated reticles for use in lithography and methods for fabricating the same
    Patent number: 8338061
    Abstract: Fluorine-passivated reticles for use in lithography and methods for fabricating and using such reticles are provided. According to one embodiment, a method for performing photolithography comprises placing a fluorine-passivated reticle between an illumination source and a target semiconductor wafer and causing electromagnetic radiation to pass from the illumination source through the fluorine-passivated reticle to the target semiconductor wafer. In another embodiment, a fluorine-passivated reticle comprises a substrate and a patterned fluorine-passivated absorber material layer overlying the substrate. According to another embodiment, a method for fabricating a reticle for use in photolithography comprises providing a substrate and forming a fluorine-passivated absorber material layer overlying the substrate.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: December 25, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Harry J. Levinson, Uzodinma Okoroanyanwu, Anna Tchikoulaeva, Rene Wirtz
  • Method and apparatus for controlling a translation lookaside buffer
    Patent number: 8341316
    Abstract: A method and apparatus are provided for controlling a translation lookaside buffer in connection with the execution of an atomic instruction. The method comprises identifying load instructions within a plurality of instructions to be executed, and placing the identified load instructions in a queue prior to execution. An atomic instruction identified in the queue is prevented from executing until the atomic instruction is the oldest instruction in the queue. The apparatus comprises a queue and a translation lookaside buffer. The queue is adapted to: identify an atomic instruction within a plurality of instructions to be executed; prevent execution of the atomic instruction until it is the oldest instruction in the queue; and send a virtual address corresponding to the atomic instruction and an atomic load signal in response to determining that the atomic instruction is the oldest instruction in the queue.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: December 25, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David Kaplan, Christopher D. Bryant, Stephen P. Thompson
  • Clock gater with programmable delay
    Patent number: 8339166
    Abstract: An integrated circuit device includes first circuitry including first logic devices and a clock tree for distributing a clock signal to the first logic devices and second circuitry including second logic devices and a clock gater operable to receive the clock signal and distribute the clock signal to the second logic devices. The clock gater comprises a programmable delay circuit.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: December 25, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Deepesh John, Sundararajan Rangarajan
  • Increased depth of drain and source regions in complementary transistors by forming a deep drain and source region prior to a cavity etch
    Patent number: 8338894
    Abstract: Deep drain and source regions of an N-channel transistor may be formed through corresponding cavities, which may be formed together with cavities of a P-channel transistor, wherein the lateral offsets of the cavities may be adjusted on the basis of an appropriate reverse spacer regime. Consequently, the dopant species in the N-channel transistor extends down to a specific depth, for instance down to the buried insulating layer of an SOI device, while at the same time providing an efficient strain-inducing mechanism for the P-channel transistor with a highly efficient overall manufacturing process flow.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: December 25, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Uwe Griebenow, Jan Hoentschel, Sven Beyer
  • Germanium MOSFET devices and methods for making same
    Patent number: 8334181
    Abstract: A double gate germanium metal-oxide semiconductor field-effect transistor (MOSFET) includes a germanium fin, a first gate formed adjacent a first side of the germanium fin, and a second gate formed adjacent a second side of the germanium fin opposite the first side. A triple gate MOSFET includes a germanium fin, a first gate formed adjacent a first side of the germanium fin, a second gate formed adjacent a second side of the germanium fin opposite the first side, and a top gate formed on top of the germanium fin. An all-around gate MOSFET includes a germanium fin, a first sidewall gate structure formed adjacent a first side of the germanium fin, a second sidewall gate structure formed adjacent a second side of the germanium fin, and additional gate structures formed on and around the germanium fin.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: December 18, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Judy Xilin An, Zoran Krivokapic, Haihong Wang, Bin Yu
  • Transistor with embedded Si/Ge material having enhanced across-substrate uniformity
    Patent number: 8334569
    Abstract: In sophisticated semiconductor devices, a strain-inducing semiconductor alloy may be positioned close to the channel region by forming cavities on the basis of a wet chemical etch process, which may have an anisotropic etch behavior with respect to different crystallographic orientations. In one embodiment, TMAH may be used which exhibits, in addition to the anisotropic etch behavior, a high etch selectivity with respect to silicon dioxide, thereby enabling extremely thin etch stop layers which additionally provide the possibility of further reducing the offset from the channel region while not unduly contributing to overall process variability.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: December 18, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Robert Mulfinger, Andy Wei, Jan Hoentschel, Casey Scott
  • Data generation and collection from a real-time system for non-real-time software simulation
    Patent number: 8332198
    Abstract: A method and apparatus for testing the functionality of a circuit design uses working system data that is recorded in real-time to stimulate and/or verify a software simulation of the circuit design that does not run in real-time. In a selected embodiment, a system for simulating and verifying a software model of a baseband module circuit design is described in connection with using real-time input and output data captured from a corresponding circuit in a reference platform. The captured real-time data may include digital baseband I/Q samples and/or extracted control data pertaining to the signal level, channel frequency, gain, output power, frequency offset, DC offset, or the like. The captured data may be regenerated for use as a stimulus for the software model of the circuit design and/or to verify the functionality of the design.
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: December 11, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael Barclay, Terry Lynn Cole, Harish Kutagulla
  • Efficient video decoding migration for multiple graphics processor systems
    Patent number: 8330762
    Abstract: Embodiments of the invention as described herein provide a solution to the problems of conventional methods as stated above. In the following description, various examples are given for illustration, but none are intended to be limiting. Embodiments include a frame processor module in a graphics processing system that examines the intra-coded and inter-coded frames in an encoded video stream and initiates migration of decoding and rendering functions to a second graphics processor from a first graphics processor based on the location of intra-coded frames in a video stream and the composition of intermediate inter-coded frames.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: December 11, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Mark S. Grossman
  • Method and apparatus for angular invariant texture level of detail generation
    Patent number: 8330767
    Abstract: A method and apparatus for angular invariant texture level of detail calculation is disclosed. The method includes a determination for a LOD that determines angular invariant LODs that result in efficient ASIC hardware implementation.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: December 11, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Konstantine Iourcha, Michael Doggett
  • Circuit for negative bias temperature instability compensation
    Patent number: 8330534
    Abstract: An integrated circuit device includes a first circuit for providing current to a first node, and a degradation compensator including a first compensation circuit coupled to the first node to provide compensation current to the first node. The degradation compensator is operable to estimate a degree of degradation in the first circuit and provide a compensation signal to the first compensation circuit to control the amount of compensation current based on the estimated degree of degradation.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: December 11, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bo Zhai, Wesley Favors, Singh Teja
  • Enhancing integrity of a high-k gate stack by protecting a liner at the gate bottom during gate head exposure
    Patent number: 8329549
    Abstract: Sophisticated gate stacks including a high-k dielectric material and a metal-containing electrode material may be covered by a protection liner, such as a silicon nitride liner, which may be maintained throughout the entire manufacturing sequence at the bottom of the gate stacks. For this purpose, a mask material may be applied prior to removing cap materials and spacer layers that may be used for encapsulating the gate stacks during the selective epitaxial growth of a strain-inducing semiconductor alloy. Consequently, enhanced integrity may be maintained throughout the entire manufacturing sequence, while at the same time one or more lithography processes may be avoided.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: December 11, 2012
    Assignee: Advanced Micro Devices Inc.
    Inventors: Sven Beyer, Frank Seliger, Gunter Grasshoff
  • Secure computer system with service guest environment isolated driver
    Patent number: 8327137
    Abstract: A virtualized computer system includes at least one guest environment (guest), a service guest environment (SG) and trusted software. The at least one guest includes at least one driver having a first private message interface. The SG includes a first USB host controller (HC) driver, which is in communication with a USB HC. The first USB HC driver includes a second private message interface. The trusted software is in communication with the guest and the SG. The trusted software includes a data intercept/routing mechanism that facilitates secure communication between at least one USB device coupled to the USB HC and the guest using the first and second private message interfaces.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: December 4, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Paul Erb, Geoffrey Strongin