Abstract: A 1.5-bit algorithmic analog-to-digital converter (ADC) generates a digital value representative of an input voltage. The ADC implements a series of conversion cycles for a conversion operation. Each conversion cycle has three sub-cycles: a scaling sub-cycle, a first sample sub-cycle, and a second sample sub-cycle. In the scaling sub-cycle, the residual voltage from the previous conversion cycle is doubled to generate a first voltage. In the first sample sub-cycle, a first bit of a corresponding bit pair is determined based on the polarity of the first voltage. The first voltage is either increased or decreased by a reference voltage based on the polarity of the first voltage to generate a second voltage. In the second sample sub-cycle, a second bit of the corresponding bit pair is determined based on the polarity of the second voltage.

Abstract: A method for determining a predicted soft error rate (SER) for an integrated circuit device design includes calculating the SER based on a predicted amount of charge imparted by a one or more particles to the integrated circuit device based on the design. The SER is further based on a predicted sensitivity level of a region of the integrated circuit device to the charge imparted by the one or more particles, and can also be based on the energy spectrum of the particles.

Abstract: A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gate conductor and the first spacers as a mask, at least extension regions are implanted in the semiconductor region and dummy spacers are formed extending outward from the first spacers. Using the dummy spacers as a mask, the semiconductor region is etched to form recesses having at least substantially straight walls extending downward from the major surface to a bottom surface, such that a substantial angle is defined between the bottom surface and the walls. Subsequently, the process is continued by epitaxially growing regions of stressed monocrystalline semiconductor material within the recesses.

Abstract: Density-conforming vertical plate capacitors exhibiting enhanced capacitance and methods for fabricating density-conforming vertical plate capacitors exhibiting enhanced capacitance are provided. An embodiment of the density-conforming vertical plate capacitor comprises a first conductive interconnect and a second conductive interconnect. The second conductive interconnect overlies the first conductive interconnect and is substantially aligned with the first conductive interconnect. A via bar electrically couples the first conductive interconnect and the second conductive interconnect. The via bar has a width and a length that is larger than the width and contributes to the capacitance of the vertical plate capacitor.

Abstract: Achieving better uniformity of temperature on an integrated circuit while performing burn-in can result in reduced burn-in time and more uniform acceleration. One way to achieve better temperature uniformity is to control dynamic power in the core and cache by operating at different frequencies and increasing switching activity in the cache(s) during burn-in by changing operation of the cache so that during burn-in a plurality of memory locations in the cache(s) are accessed simultaneously, thereby increasing activity in the cache to achieve higher power utilization in the cache during burn-in.

Abstract: The present invention provides a method and apparatus to restore the operating system of a personal internet communicator (PIC) to a “known good” operational state in the event of a catastrophic failure. In an embodiment of the invention, the hard drive of the personal internet communicator is organized in three partitions: 1) a partition for the operating system and related files; 2) a user data partition; and 3) a “restore” partition. The restore partition is hidden by modifying the type of partition that can be detected by the user or any operating system. Upon a catastrophic failure, the system can be returned to an operational state by performing a sector-by-sector restoration to copy an image of the operating system and related system files back to the operating system partition. In various embodiments of the invention, the PIC system state is continuously monitored by a “registry sniffing” routine that maintains a file containing data corresponding to the system state of the PIC.

Abstract: An interconnect structure in a semiconductor device may be formed to include a number of segments. Each segment may include a first metal. A barrier structure may be located between the plurality of segments to enable the interconnect structure to avoid electromigration problems.

Abstract: By forming a conductive material within an etch mask for an anisotropic etch process for patterning openings, such as vias, in a dielectric layer of a metallization structure, the probability for arcing events may be reduced, since excess charge may be laterally distributed. For example, an additional sacrificial conductive layer may be formed or an anti-reflecting coating (ARC) may be provided in the form of a conductive material in order to obtain the lateral charge distribution.

Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on a training signal. For instance, the method can include configuring the memory device in a training mode of operation. The method can also include determining a write timing window between a signal on a data bus and a write clock signal based on the training signal. Further, the method includes adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.

Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on results of an error detection function. For instance, the method can include determining a write timing window between a signal on a data bus and a write clock signal based on the results of the error detection function. The method can also include adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.

Abstract: By providing two or more consumable electrodes within a single reactor vessel, an alloy having a high degree of chemical ordering may be deposited in situ in that the current flows of the individual consumable electrodes are controlled to obtain a substantially layered deposition of the two or more metals. Hence, especially in copper-based metallization layers, the advantage of enhanced resistance against electromigration offered by alloys may be achieved without unduly reducing the overall conductivity.

Abstract: During the patterning of via openings in sophisticated metallization systems of semi-conductor devices, the opening may extend through a conductive cap layer and an appropriate ion bombardment may be established to redistribute material of the underlying metal region to exposed sidewall portions of the conductive cap layer, thereby establishing a protective material. Consequently, in a subsequent wet chemical etch process, the probability for undue material removal of the conductive cap layer may be greatly reduced.

Abstract: A microelectronic structure and a method for fabricating the microelectronic structure use a dielectric layer that is located and formed upon a first conductor layer. An aperture is located through the dielectric layer. The aperture penetrates vertically into the first conductor layer and extends laterally within the first conductor layer beneath the dielectric layer while not reaching the dielectric layer, to form an extended and winged aperture. A contiguous via and interconnect may be formed anchored into the extended and winged aperture while using a plating method, absent voids.

Abstract: Fluorine-passivated reticles for use in lithography and methods for fabricating and using such reticles are provided. According to one embodiment, a method for performing photolithography comprises placing a fluorine-passivated reticle between an illumination source and a target semiconductor wafer and causing electromagnetic radiation to pass from the illumination source through the fluorine-passivated reticle to the target semiconductor wafer. In another embodiment, a fluorine-passivated reticle comprises a substrate and a patterned fluorine-passivated absorber material layer overlying the substrate. According to another embodiment, a method for fabricating a reticle for use in photolithography comprises providing a substrate and forming a fluorine-passivated absorber material layer overlying the substrate.

Abstract: A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using the available processing resources to produce resulting data, and the resulting data is passed to an input/output device.

Abstract: SOI semiconductor components and methods for their fabrication are provided wherein the SOI semiconductor components include an MOS transistor in the supporting semiconductor substrate. In accordance with one embodiment the component comprises a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The component includes source and drain regions of a first conductivity type and first doping concentration in the first semiconductor layer. A channel region of a second conductivity type is defined between the source and drain regions. A gate insulator and gate electrode overlie the channel region. A drift region of the first conductivity type is located between the channel region and the drain region, the drift region having a second doping concentration less than the first doping concentration of the first conductivity determining dopant.

Abstract: A method for forming a memory device includes forming a hard mask over a substrate, where the hard mask includes a first mask layer and a second mask layer formed over the first mask layer. The substrate is etched to form a trench. The trench is filled with a field oxide material. The second mask layer is stripped from the memory device using a first etching technique and the first mask layer is stripped from the memory device using a second etching technique, where the second etching technique is different than the first etching technique.

Abstract: By suppressing the presence of free oxygen during a cleaning process and a subsequent electrochemical deposition of a seed layer, the quality of a corresponding interface between the barrier material and the seed layer may be enhanced, thereby also improving performance and the characteristics of the finally obtained metal region. Thus, by identifying free oxygen as a main source for negatively affecting the characteristics of metals during a “direct on barrier” plating process, efficient strategies have been developed and are disclosed herein to provide a reliable technique for volume production of sophisticated semiconductor devices.

Abstract: A system and a method of operating a chemical mechanical polishing (CMP) system comprises a slurry delivering unit configured for locally varying the supply of slurry while polishing the substrate. To this end, the slurry delivering unit may comprise at least one slurry outlet over a polishing pad of the CMP system, wherein the at least one slurry outlet is controllably movable to distribute slurry over the polishing pad.

Abstract: By dividing a single chip area into individual sub-areas, a thermally induced stress in each of the sub-areas may be reduced during operation of complex integrated circuits, thereby enhancing the overall reliability of complex metallization systems comprising low-k dielectric materials or ULK material. Consequently, a high number of stacked metallization layers in combination with increased lateral dimensions of the semiconductor chip may be used compared to conventional strategies.