Patents Assigned to Advanced Micro Devices
  • Method for forming semiconductor devices with active silicon height variation
    Patent number: 8003459
    Abstract: A method for forming different active thicknesses on the same silicon layer includes masking the silicon layer and exposing selected regions of the silicon layer. The thickness of the silicon layer at the exposed regions is changed, either by adding silicon or subtracting silicon from the layer at the exposed regions. Once the mask is removed, the silicon layer has regions of different active thicknesses, respectively suitable for use in different types of devices, such as diodes and transistors.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: August 23, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David E. Brown, Hans Van Meer, Sey-Ping Sun
  • Method of forming multiple fins for a semiconductor device
    Patent number: 8003466
    Abstract: A fabrication process for a FinFET device is provided. The process begins by providing a semiconductor wafer having a layer of conductive material such as silicon. A whole-field arrangement of fins is then formed from the layer of conductive material. The whole-field arrangement of fins includes a plurality of conductive fins having a uniform pitch and a uniform fin thickness. Next, a cut mask is formed over the whole-field arrangement of fins. The cut mask selectively masks sections of the whole-field arrangement of fins with a layout that defines features for a plurality of FinFET devices. The cut mask is used to remove a portion of the whole-field arrangement of fins, the portion being unprotected by the cut mask. The resulting fin structures are used to complete the fabrication of the FinFET devices.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: August 23, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Zhonghai Shi, David Wu, Jingrong Zhou, Ruigang Li
  • Method and apparatus for keeping a virtual private network session active on a portable computer system including wireless functionality
    Patent number: 8006110
    Abstract: An apparatus for keeping a VPN session alive on a portable computer system such as a laptop computer includes a processor that executes instructions that implement application software. The laptop computer system also includes a wireless module that may communicate with a wireless network such as a wireless wide area network including wireless telephone networks, for example. In addition, the wireless module may establish a virtual private network (VPN) connection with a computer network via the wireless network. The wireless module includes a processing unit that may execute instructions that cause information to be transmitted to a host portion of the virtual private network connection at one or more predetermined times.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: August 23, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Robert Ober
  • IOMMU Architected TLB Support
    Publication number: 20110202724
    Abstract: Embodiments allow a smaller, simpler hardware implementation of an input/output memory management unit (IOMMU) having improved translation behavior that is independent of page table structures and formats. Embodiments also provide device-independent structures and methods of implementation, allowing greater generality of software (fewer specific software versions, in turn reducing development costs).
    Type: Application
    Filed: February 17, 2010
    Publication date: August 18, 2011
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Andrew G. KEGEL, Mark Hummel, Erich Boleyn
  • Interconnects with a dielectric sealant layer
    Patent number: 7998856
    Abstract: Leakage, capacitance and reliability degradation of interconnects fabricated in low-k dielectric materials, particularly porous low-k dielectric material, due to penetration by a barrier metal and/or barrier metal precursor during damascene processing is prevented by depositing a conformal, heat stable dielectric sealant layer on sidewalls of the low-k dielectric material defining the damascene opening. Embodiments include forming a dual damascene opening in a porous, low-k organosilicate layer, the organosilicate having a pendant silanol functional group, depositing a siloxane polymer having a silylating functional group which bonds with the pendant silanol group to form the sealant layer, depositing a Ta and/or TaN barrier metal layer by CVD or ALD and filling the opening with Cu or a Cu alloy.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: August 16, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventor: E. Todd Ryan
  • Method and apparatus to reduce the effect of crosstalk in a communications interface
    Patent number: 8000404
    Abstract: A technique for reducing crosstalk between communications paths includes scrambling data using scrambling functions that reduce or substantially minimize a probability that worst-case data patterns occur on communications paths adjacent to a potential victim communications path. In at least one embodiment of the invention, a method includes scrambling a plurality of data bits based at least in part on respective ones of a plurality of distinct combinations of one or more taps of a linear feedback shift register (LFSR). The plurality of data bits are scrambled for transmission during a first bit-time on corresponding ones of a plurality of adjacent communications paths.
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: August 16, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gerald R. Talbot, Paul C. Miranda
  • Rectifying and level shifting circuit
    Patent number: 7999595
    Abstract: A circuit includes a differential circuit having at least to two inputs, a first variable impedance circuit, and a second variable impedance circuit. The first variable impedance circuit is between a first branch of the differential circuit and an output. The first variable impedance circuit provides a first variable impedance. The a second variable impedance circuit is between a second branch of the differential circuit and the output. The second variable impedance circuit provides a second variable impedance. The first variable impedance and the second variable impedance vary in accordance with a voltage difference between the two inputs.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: August 16, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jinyung Namkoong, Arvind Bomdica, Ming-Ju Lee
  • Tensile strain source using silicon/germanium in globally strained silicon
    Patent number: 7999326
    Abstract: By embedding a silicon/germanium mixture in a silicon layer of high tensile strain, a moderately high degree of tensile strain may be maintained in the silicon/germanium mixture, thereby enabling increased performance of N-channel transistors on the basis of silicon/germanium material. In other regions, the germanium concentration may be varied to provide different levels of tensile or compressive strain.
    Type: Grant
    Filed: April 5, 2010
    Date of Patent: August 16, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andy Wei, Karla Romero, Manfred Horstmann
  • Void reduction in indium thermal interface material
    Patent number: 7999394
    Abstract: Thermal interface materials and method of using the same in packaging are provided. In one aspect, a thermal interface material is provided that includes an indium preform that has a first surface and a second surface opposite to the first surface, an interior portion and a peripheral boundary. The indium preform has a channel extending from the peripheral boundary towards the interior portion. The channel enables flux to liberate during thermal cycling.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: August 16, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Seah Sun Too, Hsiang Wan Liau, Janet Kirkland, Tek Seng Tan, Maxat Touzelbaev, Raj N. Master
  • Method for reducing leakage currents caused by misalignment of a contact structure by increasing an error tolerance of the contact patterning process
    Patent number: 7998823
    Abstract: By forming an additional doped region with increased junction depth at areas in which contact regions may connect to drain and source regions, any contact irregularities may be embedded into the additional doped region, thereby reducing the risk for leakage currents or short circuits between the drain and source region and the well region that may be conventionally caused by the contact irregularity. Moreover, additionally or alternatively, the surface topography of the semiconductor region and the adjacent isolation trench may be modified prior to the formation of metal silicide regions and contact plugs to enhance the lithography procedure for forming respective contact openings in an interlayer dielectric material. For this purpose, the isolation trench may be brought to an equal or higher level compared to the adjacent semiconductor region.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: August 16, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Carsten Peters, Kai Frohberg, Ralf Richter
  • Semiconductor device with isolation trench liner, and related fabrication methods
    Patent number: 7998832
    Abstract: A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: August 16, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Richard J. Carter, George J. Kluth, Michael J. Hargrove
  • Error detection in high-speed asymmetric interfaces
    Patent number: 7996731
    Abstract: A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component controls many operations of the second component, including receiving a signature from the second component over an existing line of the interface. The signature received is compared to a signature stored by the first component. Both signatures correspond to a transaction over the interface. Based on the comparison, the first component determines whether the transaction was successful, and directs the second component as necessary.
    Type: Grant
    Filed: November 1, 2006
    Date of Patent: August 9, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Joseph Macri, Stephen Morein, Claude Gauthier, Ming-Ju E. Lee, Lin Chen
  • Enhanced stress transfer in an interlayer dielectric by using an additional stress layer above a dual stress liner in a semiconductor device
    Patent number: 7994059
    Abstract: By forming an additional stressed dielectric material after patterning dielectric liners of different intrinsic stress, a significant increase of performance in transistors may be obtained while substantially not contributing to patterning non-uniformities during the formation of respective contact openings in highly scaled semiconductor devices. The additional dielectric layer may be provided with any type of intrinsic stress, irrespective of the previously selected patterning sequence.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: August 9, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ralf Richter, Martin Gerhardt, Martin Mazur, Joerg Hohage
  • Sidewall graphene devices for 3-D electronics
    Patent number: 7993986
    Abstract: A device is provided that includes a structure having a sidewall surface, a layer of material provided on the sidewall surface, and a device structure provided in contact with the layer of material. Fabrication techniques includes a process that includes forming a structure having a sidewall surface, forming a layer of material on the sidewall surface, and forming a device structure in contact with the layer of material, where the device structure and the layer of material are components of a device.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: August 9, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: An Chen, Zoran Krivokapic
  • Integrated circuit contact system
    Patent number: 7994047
    Abstract: An integrated circuit contact system is provided including forming a contact plug in a dielectric and forming a first barrier layer in a trench in the dielectric and on the contact plug. Further, the system includes removing a portion of the first barrier layer from the bottom of the first barrier layer and depositing the portion of the first barrier layer on the sidewall of the first barrier layer, and forming a second barrier layer over the first barrier layer and filling a corner area of the trench.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: August 9, 2011
    Assignees: Spansion LLC, Advanced Micro Devices, Inc.
    Inventors: Christy Mei-Chu Woo, Ning Cheng, Huade Walter Yao
  • Gate dielectrics of different thickness in PMOS and NMOS transistors
    Patent number: 7994037
    Abstract: By providing a gate dielectric material of increased thickness for P-channel transistors compared to N-channel transistors, degradation mechanisms, such as negative bias threshold voltage instability, hot carrier injection and the like, may be reduced. Due to the enhanced reliability of the P-channel transistors, overall production yield for a specified quality category may be increased, due to the possibility of selecting narrower guard bands for the semiconductor device under consideration.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: August 9, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Martin Trentzsch, Karsten Wieczorek, Edward Ehrichs
  • Semiconductor devices having faceted silicide contacts, and related fabrication methods
    Patent number: 7994014
    Abstract: The disclosed subject matter relates to semiconductor transistor devices and associated fabrication techniques that can be utilized to form silicide contacts having an increased effective size, relative to conventional silicide contacts. A semiconductor device fabricated in accordance with the processes disclosed herein includes a layer of semiconductor material and a gate structure overlying the layer of semiconductor material. A channel region is formed in the layer of semiconductor material, the channel region underlying the gate structure. The semiconductor device also includes source and drain regions in the layer of semiconductor material, wherein the channel region is located between the source and drain regions. Moreover, the semiconductor device includes facet-shaped silicide contact areas overlying the source and drain regions.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: August 9, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Frank Bin Yang, Rohit Pal, Michael J. Hargrove
  • System and method for controlling an electrochemical etch process
    Patent number: 7993936
    Abstract: By evaluating a status signal on the basis of a fault detection classification mechanism in an electrochemical etch tool, a corresponding failure status of the tool may be obtained for each single substrate, thereby significantly reducing the risk of significant yield loss compared to conventional strategies. The fault detection and classification mechanism may be advantageously applied to the electrochemical removal of underbump metallization layers during the formation of solder bump structures.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: August 9, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kerstin Siury, Niels Rackwitz, Joern Schnapke, Frank Kuechenmeister
  • Stress transfer by sequentially providing a highly stressed etch stop material and an interlayer dielectric in a contact layer stack of a semiconductor device
    Patent number: 7994072
    Abstract: By forming two or more individual dielectric layers of high intrinsic stress levels with intermediate interlayer dielectric material, the limitations of respective deposition techniques, such as plasma enhanced chemical vapor deposition, may be respected while nevertheless providing an increased amount of stressed material above a transistor element, even for highly scaled semiconductor devices.
    Type: Grant
    Filed: April 24, 2008
    Date of Patent: August 9, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Joerg Hohage, Michael Finken, Ralf Richter
  • Method of forming finned semiconductor devices with trench isolation
    Patent number: 7994020
    Abstract: A method of manufacturing a semiconductor device structure, such as a FinFET device structure, is provided. The method begins by providing a substrate comprising a bulk semiconductor material, a first conductive fin structure formed from the bulk semiconductor material, and a second conductive fin structure formed from the bulk semiconductor material. The first conductive fin structure and the second conductive fin structure are separated by a gap. Next, spacers are formed in the gap and adjacent to the first conductive fin structure and the second conductive fin structure. Thereafter, an etching step etches the bulk semiconductor material, using the spacers as an etch mask, to form an isolation trench in the bulk semiconductor material. A dielectric material is formed in the isolation trench, over the spacers, over the first conductive fin structure, and over the second conductive fin structure.
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: August 9, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ming-ren Lin, Zoran Krivokapic, Witek Maszara