Abstract: A semiconductor component having a composite via structure with an enhanced aspect ratio and a method for manufacturing the semiconductor component. Vias having a first aspect ratio are formed in a contact layer disposed on a semiconductor substrate and filled with a metal. The metal is planarized and a dielectric layer is formed over the contact layer. Via extension structures having the same aspect ratio as those in the contact layer are formed in the dielectric layer and aligned with the vias in the contact layer. The vias in the dielectric layer are filled with metal and the metal is planarized. The contact vias in the contact layer and the dielectric layer cooperate to form a composite via structure having the enhanced aspect ratio. Additional dielectric layers having via structures can be included in the composite contact structure to further enhance the aspect ratio of the via structure.

Abstract: An apparatus includes a central processing unit having an output to provide a status indicator, a graphics controller having an output coupleable to a display interface, a cache comprising a plurality of cache lines, and memory controller having an input to receive the status indicator. The memory controller is configured to disable allocation of cache lines of the cache for cache misses for data requests from the graphics controller in response to the status indicator indicating the central processing unit is in an active mode. The memory controller further is configured to enable allocation of cache lines of the cache for cache misses for data requests from the graphics controller in response to the status indicator indicating the central processing unit is in an idle mode.

Abstract: A substrate comprising a first transistor element and a second transistor element is provided. A layer of a material is deposited over the first transistor element and the second transistor element. A portion of the layer of material is modified, which may be done, e.g., by irradiating the portion with ions or performing an isotropic etching process to reduce its thickness. An etching process adapted to remove the modified portion of the layer of material more quickly than an unmodified portion of the layer located over the second transistor element is performed.

Abstract: Disclosed are a method of reducing biological contamination in an immersion lithography system and an immersion lithography system configured to reduce biological contamination. A reflecting element and/or an irradiating element is used to direct radiation to kill biological contaminates present with respect to at least one of i) a volume adjacent a final element of the projection system or ii) an immersion medium supply device disposed adjacent the final element.

Abstract: A computer graphics processing system includes a graphics processor and a computer memory responsive to the graphics processor. The computer memory includes an image depth buffer and a hierarchical image depth buffer. The hierarchical image depth buffer contains data items that identify a nearest depth value and a farthest depth value for a plurality of image depth buffer entries associated with a plurality of corresponding pixels.

Abstract: The present invention provides a nitrogen-free ARC/capping layer in a low-k layer stack, which, in particular embodiments, is comprised of carbon-containing silicon dioxide, wherein the optical characteristics are tuned to conform to the 193 nm lithography. Moreover, the ARC/capping layer is directly formed on the low-k material, thereby also preserving the integrity thereof during an etch and chemical mechanical polishing process.

Abstract: During the formation of a transistor element, sidewalls spacers are removed or at least partially etched back after ion implantation and silicidation, thereby rendering the mechanical coupling of a contact etch stop layer to the underlying drain and source regions more effective. Hence, the mechanical stress may be substantially induced by the contact etch step layer rather than by a combination of the spacer elements and the etch stop layer, thereby significantly facilitating the stress engineering in the channel region. By additionally performing a plasma treatment, different amounts of stress may be created in different transistor devices without unduly contributing to process complexity.

Abstract: In one embodiment, a method of controlling the across-chip line-width variation (ACLV) on a semiconductor integrated circuit includes forming an ACLV controlled region including a plurality of semiconductor devices each having a gate structure and arranging the plurality of semiconductor devices to have a substantially uniform spacing between each gate structure. The method also includes forming a decoupling capacitor region adjacent to the ACLV controlled region. The decoupling capacitor region may include a plurality of capacitor structures each having a conductive structure, such as a polysilicon electrode, for example.

Abstract: A microprocessor is configured to provide port arbitration in a register file. The microprocessor includes a plurality of functional units configured to collectively operate on a maximum number of operands in a given execution cycle, and a register file providing a number of read ports that is insufficient to provide the maximum number of operands to the plurality of functional units in the given execution cycle. The microprocessor also includes an arbitration logic coupled to allocate the read ports of the register file for use by selected functional units during the given execution cycle.

Abstract: A method, apparatus, and a system for determining a control thread based upon a process result are provided. At least one post-process parameter is received. The post parameter relates to a first workpiece upon which a plurality of processes have been performed by a plurality of processing tools. A combination of at least a portion of the plurality of processing tools is selected based upon the post-process parameter.

Abstract: The present invention provides an integrated circuit design system, comprising providing a design system in a computer system, providing a layout design tool coupled to the design system, wherein the layout design tool creates an interconnect structure to satisfy electromigration criteria, and manipulating a design database within the design system.

Abstract: Methods and apparatus for checking layouts of circuit features are provided. In one aspect, a method of designing a layout for a circuit feature is provided that includes deriving a function which relates a size and a plurality of aerial image parameters of the circuit feature to a probability of a printing fault in using a lithographic process to pattern the circuit feature. A layout for the circuit feature is created. The function is used to determine a probability of a printing fault in using the lithographic process to pattern the circuit feature and adjust the layout of the circuit feature as necessary in view of the determined probability of printing fault.

Abstract: A method of producing a layout representation corresponding to an integrated circuit (IC) device design can include generating an initial layout representation in accordance with a predetermined set of design rules and simulating how structures within the initial layout representation will pattern on a wafer. Based on the simulation, portions of the layout representation, which include structures demonstrating poor manufacturability and/or portions of the layout representation in which extra manufacturability margin is present, can be identified. Portions of the layout representation including structures demonstrating poor manufacturability and/or in which extra manufacturability margin is present can be modified to optimize the layout representation.

Abstract: A wireless computer system (30) is formed to have a host section (31) and a wireless hardware section (40). A first portion of a transmission frame is formed in system memory (36) of a host section (31) and a second portion of the transmission frame is formed in the wireless hardware section (40). The wireless hardware section (40) begins transmitting the first transmission frame portion while downloading the second transmission frame portion from the system memory (36) into the wireless hardware section (40). Bus latencies are masked by at least overlapping transmitting the first portion of the transmit frame while downloading the second portion.

Abstract: A semiconductor structure comprises a stress sensitive element. A property of the stress sensitive element is representative of a stress in the semiconductor structure. Additionally, the semiconductor structure may comprise an electrical element. The stress sensitive element and the electrical element comprise portions of a common layer structure. Analyzers may be adapted to determine a property of the stress sensitive element being representative of a stress in the semiconductor structure and a property of the electrical element. The property of the stress sensitive element may be determined and the manufacturing process may be modified based on the determined property of the stress sensitive element. The property of the electrical element may be related to the property of the stress sensitive element in order to investigate an influence of stress on the electrical element.

Abstract: A receiver, an integrated circuit chip and a method are provided for estimating the power of a digitally modulated signal received by the receiver in a communication system. The method comprises determining in-phase and quadrature-phase values of a phase constellation system relating to the received signal, calculating at least one modified in-phase value and at least one modified quadrature-phase value relating to the phase constellation system rotated by a predetermined angle, and determining absolute values of the in-phase and quadrature-phase values and the modified in-phase and quadrature-phase values. The method further comprises identifying the maximum of the absolute values, and determining a power estimate of the received signal based on the identified maximum value. The provided technique may allow for estimating the power of a digitally modulated signal in a simple and less complex implementation.

Abstract: An integrated circuit includes multiple layers. A semiconductor-on-insulator (SOI) wafer can be used to house transistors. Two substrates or wafers can be bonded to form the multiple layers. A strained semiconductor layer can be between a silicon germanium layer and a buried oxide layer. A hydrogen implant can provide a breaking interface to remove a silicon substrate from the silicon germanium layer.

Abstract: A memory device having a metal nanocrystal charge storage structure and a method for its manufacture. The memory device may be manufactured by forming a first oxide layer on the semiconductor substrate, then disposing a porous dielectric layer on the oxide layer and disposing a second oxide layer on the porous dielectric layer. A layer of electrically conductive material is formed on the second layer of dielectric material. An etch mask is formed on the electrically conductive material. The electrically conductive material and the underlying dielectric layers are anisotropically etched to form a dielectric structure on which a gate electrode is disposed. A metal layer is formed on the dielectric structure and the gate electrode and treated so that portions of the metal layer diffuse into the porous dielectric layer. Then the metal layer is removed.

Abstract: By performing a first common etch process for forming a via opening and a delineation trench or open area in a metallization layer with different removal rates, the etch front in the delineation trench or open area may be delayed, thereby significantly reducing the probability of wafer arcing. Subsequently, the delineation trench or open area may be etched down to the respective etch stop layer in a further common etch process, during which a trench is formed above the via opening.

Abstract: A system that facilitates extraction of line edge roughness measurements that are independent of proprietorship of a metrology device comprises a structure patterned onto silicon with known line edge roughness values associated therewith. A metrology device obtains line edge roughness measurements from the structure, and a correcting component generates an inverse function based upon a comparison between the known line edge roughness values and the measured line edge roughness values. The metrology device can thereafter measure line edge roughness upon a second structure patterned on the silicon, and the inverse function can be applied to such measured line edge roughness values to enable obtainment of line edge roughness measurements that are independent of proprietorship of the metrology device.