Abstract: Methods and systems are disclosed that allow an adjustment of a product parameter, such as operating speed, of a circuit element, such as a field effect transistor, during the fabrication of the device. A manufacturing process downstream of a first controlled process is controlled by a superior control scheme in response to the measurement data of the first and second processes and on the basis of a sensitivity function, which describes the effect a variation of the product parameter generates in the measurement data. The superior control scheme may provide a compensated target value for the downstream process.

Abstract: The present invention provides a method that includes determining a jeopardy count associated with at least one processing tool and selecting at least one wafer based upon the jeopardy count, the at least one wafer having been processed by the at least one processing tool.

Abstract: A memory device includes multiple fins formed adjacent to one another, a source region, a drain region, a gate, a wordline, and a bitline contact. At least one of the multiple fins is doped with a first type of impurities and at least one other one of the fins is doped with a second type of impurities. The source region is formed at one end of each of the fins and the drain region is formed at an opposite end of each of the fins. The gate is formed over two of the multiple fins, the wordline is formed over each of the multiple fins, and a bitline contact is formed adjacent at least one of the multiple fins.

Abstract: An epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure. The channel layer may be undoped or slightly doped, as required, so that the finally obtained dopant concentration in the channel layer is significantly reduced compared to a conventional device to thereby provide a retrograde dopant profile in a channel region of a field effect transistor. Additionally, a barrier diffusion layer may be provided between the well structure and the channel layer to reduce up-diffusion during any heat treatments carried out after the formation of the channel layer. The final dopant profile in the channel region may be adjusted by the thickness of the channel layer, the thickness and the composition of the diffusion barrier layer and any additional implantation steps to introduce dopant atoms in the channel layer.

Abstract: According to one exemplary embodiment, a method includes planarizing a layer of polysilicon situated over field oxide regions on a substrate to form polysilicon segments, where the polysilicon segments have top surfaces that are substantially planar with top surfaces of the field oxide regions, and where the field oxide regions have a first height and the polysilicon segments have a first thickness. The method further includes removing a hard mask over a peripheral region of the substrate. According to this exemplary embodiment, the method further includes etching the polysilicon segments to cause the polysilicon segments to have a second thickness, which causes the top surfaces of the polysilicon segments to be situated below the top surfaces of the field oxide regions. The polysilicon segments can be etched by using a wet etch process. The polysilicon segments are situated in a core region of the substrate.

Abstract: A memory device with multi-bit memory cells and method of making the same uses self-assembly to provide polymer memory cells on the contacts to a transistor array. Employing self-assembly produces polymer memory cells at the precise locations of the contacts of the transistor array. The polymer memory cells change resistance values in response to electric current above a specified threshold value. The memory cells retain the resistivity values over time.

Abstract: A computer system may include multiple processing nodes, one or more of which may be coupled to separate memories which may form a distributed memory system. The processing nodes may include caches, and the computer system may maintain coherency between the caches and the distributed memory system. Particularly, the computer system may implement a flexible probe command/response routing scheme. The scheme may employ an indication within the probe command which identifies a receiving node to receive the probe responses. For example, probe commands indicating that the target or the source of transaction should receive probe responses corresponding to the transaction may be included. Probe commands may specify the source of the transaction as the receiving node for read transactions (such that dirty data is delivered to the source node from the node storing the dirty data).

Abstract: A header detection technique for WLAN (Wireless Local Area Network) receivers is provided. The WLAN receiver comprises a signal processing unit that has analog circuitry and digital circuitry. There is further provided a header detection circuit for detecting a header in a received signal. The header detection circuit is comprised in the analog circuitry. In an embodiment, digital circuitry may be woken up based on a header detect signal that is generated by the header detection circuit. The embodiments may reduce the power consumption of the receiver, and the false detection rate.

Abstract: A power subsystem including a mechanism for satisfying a predetermined power limit in a computer system. The power subsystem may include a split power supply and a voltage regulator. The split power supply may include at least a first voltage supply line and a second voltage supply line. The voltage supply lines may be closely matched voltage sources, each configured to provide relatively the same voltage amount. The voltage regulator may step-down a voltage provided by each of the first and second voltage supply lines to generate a desired voltage for a load. The first voltage supply line may be isolated from the second voltage supply line to limit power provided through either the first or the second voltage supply line from exceeding a predetermined power limit. The predetermined power limit may be a power limit set by U.L. standard #60950, i.e., 250 Watts.

Abstract: A semiconductor memory device may include an intergate dielectric layer of high-K dielectric materials interposed between a charge storing layer and a control gate. The high-K materials may be deposited in such a manner that the materials are gradually graded with respect to one another.

Abstract: A method of routing packets includes receiving a first packet, where the first packet has a first ordering requirement with respect to a prior packet that was received before the first packet, allocating a first entry that corresponds to the first packet in a scheduler, where the first entry includes a first indication of the first ordering requirement, and in response to the first indication, selecting the first entry corresponding to the first packet if one or more first resources used by the first packet and one or more second resources that are used by the prior packet but not by the first packet are available. As long as older entries whose resources are available are selected before newer entries, the first entry will be selected after the prior packet's entry due to the inclusion of the first indication in the first entry.

Abstract: A WLAN (Wireless Local Area Network) communication device comprising a WLAN frequency synthesizer for generating a synthesizer signal suitable for modulating a transmission signal and/or demodulating a reception signal and corresponding methods and integrated circuit chips are provided. The WLAN frequency synthesizer comprises a reference oscillator for generating a first reference clock signal, a fractional-N PLL (Phase-Locked Loop) unit for receiving a second reference clock signal and converting the second reference clock signal into the synthesizer signal, and a frequency multiplier for receiving the first reference clock signal and converting the first reference clock signal into the second reference clock signal to be forwarded to the fractional-N PLL unit by multiplying the frequency of the first reference clock signal by a multiplication factor. Embodiments may provide shorter settling times and/or enhanced spurious suppression of the fractional-N PLL unit.

Abstract: A network device identifies priority level information for data frames it receives. The network device includes input ports, a memory, an action generator, and a port vector queue. The input ports receive the data frames. Each of the received data frames specifies one or more classes of service. The memory stores priority level information corresponding to each of the classes of service. The action generator generates an action tag for each of the received data frames. The port vector queue uses the action tag from the action generator for each of the received data frames to access the memory to identify the priority level information associated with the received data frame.

Abstract: Systems and methodologies are provided that account for surface variations of a wafer by adjusting grating features of an imprint lithography mask. Such adjustment employs piezoelectric elements as part of the mask, which can change dimensions (e.g., a height change) and/or move when subjected to an electric voltage. Accordingly, by regulating the amount of electric voltage applied to the piezoelectric elements a controlled expansion for such elements can be obtained, to accommodate for topography variations of the wafer surface.

Abstract: The present invention is generally directed to various methods and systems for dynamically controlling metrology work in progress. In one illustrative embodiment, the method comprises providing a metrology control unit that is adapted to control metrology work flow to at least one metrology tool, identifying a plurality of wafer lots that are in a metrology queue wherein the wafer lots are intended to be processed in at least one metrology tool, and wherein the metrology control unit selects at least one of the wafer lots for metrology processing in the at least one metrology tool and selects at least one other of the plurality of wafer lots to be removed from the metrology queue based upon the metrology processing of the selected at least one wafer lot in the at least one metrology tool.

Abstract: In one embodiment, a node comprises, integrated onto a single integrated circuit chip (in some embodiments), a plurality of processor cores and a node controller coupled to the plurality of processor cores. The node controller is coupled to receive an external request transmitted to the node, and is configured to transmit a corresponding request to at least a subset of the plurality of processor cores responsive to the external request. The node controller is configured to receive respective responses from each processor core of the subset. Each processor core transmits the respective response independently in response to servicing the corresponding request and is capable of transmitting the response on different clock cycles than other processor cores. The node controller is configured to transmit an external response to the external request responsive to receiving each of the respective responses.

Abstract: A host channel adapter includes a transport layer module, a link layer module, and buffer memory having memory portions configured for storage of transmit data packets output by the transport layer module for transmission by the link layer module on identified virtual lanes. The transport layer module is configured for identifying a virtual lane for each transmit data packet, and for storing the transmit data packet in the corresponding memory portion assigned to the corresponding identified virtual lane. Hence, the transmit data packets output by the transport layer module are stored in the memory portions based on their respective identified virtual lanes, where each memory portion stores the transmit data packets for the corresponding identified virtual lane. The link layer module retrieves the transmit data packets from a selected memory portion corresponding to a currently-serviced virtual lane based on a prescribed virtual lane arbitration.

Abstract: A baseboard management controller (BMC) integrated circuit hosts a BIOS ROM interface. The BMC includes a bus interface responsive to an access to an address range associated with host operations, e.g., an address range associated with BIOS. The BMC includes an interface coupled to communicate with a remote computer for receiving BIOS updates and/or a BIOS patches from the remote computer. Multiple computers may each include a BMC-hosted BIOS ROM interface and may be coupled to a remote computer for communicating BIOS information between the BMCs and the remote computer.

Abstract: An OFDM receiver configured for measuring frequency error based on comparing prescribed pilot tones from a prescribed group of consecutive symbols in a received OFDM signal. A complex conjugate generator is configured for generating complex conjugates of the prescribed pilot tones of a first subgroup of the consecutive symbols. A multiplier is configured for generating a complex pilot product, for each symbol subgroup position, by multiplying the pilot tones of a second subgroup symbol at the corresponding symbol subgroup position with the respective complex conjugates of the first subgroup symbol at the corresponding symbol subgroup position. A complex summation circuit sums the complex pilot products of the symbol subgroup positions to obtain an accumulated complex value. A error calculator calculates the frequency error from the accumulated complex value for use in correcting frequency offset.

Abstract: A communication processor comprises a data link layer parser circuit (310) and a plurality of network layer parser circuits (322, 326). The data link layer parser circuit (310) receives a data link layer frame, and removes a data link layer header therefrom to provide a network layer frame as an output. Each network layer parser circuit corresponds to a different network layer protocol, and is selectively activated to receive the network layer frame and to process a network layer header therefrom to provide a transport layer frame as an output. The data link layer parser circuit (310) further examines a portion of the network layer frame to determine which of the plurality of network protocols is used. The data link layer parser circuit (310) activates a corresponding one of the plurality of network layer parser circuits (322, 326) in response, while keeping another one of the plurality of network layer parser circuits (322, 326) inactive.