Abstract: By forming a non-oxidizable liner in isolation trenches, the creation of compressive stress may be significantly reduced, wherein, in illustrative embodiments, silicon nitride may be used as liner material. For this purpose, the etch behavior of the silicon nitride may be efficiently modified on the basis of an appropriate surface treatment, thereby providing a high degree of material integrity during a subsequent etch process for removing non-modified portions of silicon nitride, which may also be used as an efficient CMP stop layer.

Abstract: A split-transaction bus decoder receives a plurality of packets, the plurality of packets including a request packet and a response packet, wherein the request packet includes an address and a request tag; and the response packet includes a command, a response tag, and data. Upon receipt of the request packet, the decoder stores the address and the request tag. Upon receipt of the response packet, the decoder matches the response tag to the request tag. The decoder produces a decoded packet including the address of the request packet and the command and the data of the response packet.

Abstract: An improved data communication receiver technique is provided which avoids demodulation errors due to abrupt phase changes. A receiver is provided for processing an incoming digitized signal. The receiver comprises a pre-processing portion, a phase error correction unit and a signal evaluation unit. The pre-processing portion is adapted to process the digitized signal for providing a non-coherent pre-processed signal. The phase error correction unit is adapted to correct a phase error of the non-coherent pre-processed signal and output a coherent signal. The signal evaluation unit is adapted to extract information from the non-coherent pre-processed signal and to output a data signal representing the extracted information. The phase error correction unit and said signal evaluation unit are configured to operate simultaneously for a predetermined time.

Abstract: A channel estimator is configured for determining a gain adjustment for a received wireless signal having a prescribed plurality of tones. The channel estimator is configured for generating, for each of the tones, a corresponding pseudo power value representing a detected power level for the corresponding tone. An accumulated pseudo power value is obtained based on accumulating the respective pseudo power values of the prescribed plurality of tones. Each of the pseudo power values is selectively adjusted by an adjustment factor based on a determined difference between the accumulated pseudo power value relative to an expected accumulated power level relative to a prescribed dynamic range. The pseudo power values are then output for decoding of data modulated at the respective tones.

Abstract: According to one exemplary embodiment, a method of fabricating a bitline in a memory array includes forming a trench in a substrate, where the trench has sidewalls and a bottom surface. The method further includes performing a selective epitaxial process to partially fill the trench with selective epitaxially grown silicon, where the selective epitaxially grown silicon is situated on the sidewalls and bottom surface of the trench. The selective epitaxially grown silicon is doped in the selective epitaxial process. The method further includes performing a silicon reflow process to cause the selective epitaxially silicon to be redistributed in the trench. The method further includes performing a number of selective epitaxial process/silicon reflow process cycles to substantially fill the trench with the selective epitaxially grown silicon. The method further includes extending a top surface of the selective epitaxially grown silicon in the trench above an ONO stack to form the bitline.

Abstract: Methods for forming asymmetric gate structures comprising spacer elements disposed on the opposed sides of a gate electrode and having a different width are disclosed. The asymmetric gate structures are employed to form an asymmetric design of a halo region and extension regions of a field effect transistor using a symmetric implantation scheme, or to further enhance the effectiveness of asymmetric implantation schemes. The transistor performance may be significantly enhanced for a given basic transistor architecture. In particular, a large overlap area may be created at the source side with a steep concentration gradient of the PN junction due to the provision of the halo region, whereas the drain overlap may be significantly reduced or may even be completely avoided to further enhance the transistor performance.

Abstract: A phase-locked loop (PLL) frequency synthesizer capable of being tuned in small step sizes. The PLL frequency synthesizer includes a PLL circuit. A phase-locked loop (PLL) frequency synthesizer includes a PLL core and a feedback frequency divider. The PLL core receives an F(in) signal and generates a plurality of multiphase output signals having an F2 frequency, where F2=(in)(P+?p). The feedback frequency divider receives the plurality of multiphase output signals and generates a feedback signal having a frequency of F2/(P+?p), where P is an integer and ?p is a fractional value less than one.

Abstract: By using a disposable spacer approach for forming drain and source regions prior to an amorphization process for re-crystallizing a semiconductor region in the presence of a stressed spacer layer, possibly in combination with enhanced anneal techniques, such as laser and flash anneal processes, a more efficient strain-generating mechanism may be provided. Furthermore, the spacer for forming the metal silicide may be provided with reduced width, thereby positioning the respective metal silicide regions more closely to the channel region. Consequently, an overall enhanced performance may be obtained on the basis of the above-described techniques.

Abstract: A circuit for implementing memory arrays using a global bitline domino read/write scheme. The memory circuit includes a plurality of cells each configured to store a bit of data. The memory circuit further includes a plurality of local bitlines, wherein each cells is coupled to one of the local bitlines. Each of the plurality of local bitlines is a differential bitline having a signal path and a complementary signal path which are cross-coupled by a pair of transistors.

Abstract: A chromeless phase-shift mask (CPM) for imaging sub-100 nm contact holes and a method of making the same are disclosed. The CPM includes a plurality of features formed on a substrate and a plurality of suppressors formed on the substrate. Light energy passing through the plurality of suppressors substantially reduces an interference generated by light energy passing through features within an optical proximity of each other, thereby significantly improving contrast and depth of focus. The plurality of features can be formed in a grid pattern, and the suppressors can be formed in adjacent corners of each feature. The size and location of the suppressors can be varied with respect to the features to obtain a desired image.

Abstract: By removing an outer spacer, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, a high degree of process compatibility with conventional processes is obtained, while at the same time a contact liner layer may be positioned more closely to the channel region, thereby allowing a highly efficient stress transfer mechanism for creating a corresponding strain in the channel region.

Abstract: A test structure includes first and second combs, at least a first pair of base nodes, and a second pair of finger nodes. The first comb includes a first base and a first plurality of fingers extending from the first base. The second comb includes a second base and a second plurality of fingers extending from the second base. At least a portion of the first and second pluralities of fingers are interleaved. The first pair of base nodes extend from the first base. The second pair of finger nodes extend from a first finger of the first plurality of fingers.

Abstract: The present invention relates to a system and method of inspecting a semiconductor sample. A plurality of scans of the semiconductor sample are recorded. Each of the scans comprises a spatially resolved measurement of a property of interest. At least one cross-correlation is calculated between at least two of the plurality of scans. For each of the plurality of scans, a respective shift value is calculated based on the at least one cross-correlation. The scans are superimposed with each other. In the superposition, each of the scans is shifted by the respective shift value. The shift values can be adapted to compensate a drift of the semiconductor sample which occurs while the scans are recorded. Hence, the present invention helps overcome problems caused by the drift.

Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode over a substrate, implanting dopants into the substrate and activating the dopants using laser thermal annealing. During annealing, the laser and substrate are moved relative to one another, and the movement of the laser and the substrate relative to one another does not pause between and during activating one portion of the source/drain regions and activating another portion of the source/drain regions. Each pulse from the laser can respectively irradiate different portions of the source/drain regions, and a spot area of the laser is less than 50 millimeter2.

Abstract: Methods are provided for fabricating a CMOS device having a silicon substrate including a first N-type region and a second P-type region. The method includes the steps of forming a first gate electrode overlying the first N-type region and a second gate electrode overlying the second P-type region. P-type source and drain regions are ion implanted into the first N-type region, and N-type source and drain regions are ion implanted into the second P-type region. First silicide regions, spaced apart from the first gate electrode by a first distance, are formed contacting the P-type source and drain regions, and second silicide regions, spaced apart from the second gate electrode by a second distance less than the first distance, are formed contacting the N-type source and drain regions.

Abstract: A hierarchical encoding format for coding repairs to devices within a computing system. A device, such as a cache memory, is logically partitioned into a plurality of sub-portions. Various portions of the sub-portions are identifiable as different levels of hierarchy of the device. A first sub-portion may corresponds to a particular cache, a second sub-portion may correspond to a particular way of the cache, and so on. The encoding format comprises a series of bits with a first portion corresponding to a first level of the hierarchy, and a second portion of the bits corresponds to a second level of the hierarchy. Each of the first and second portions of bits are preceded by a different valued bit which serves to identify the hierarchy to which the following bits correspond. A sequence of repairs are encoded as string of bits. The bit which follows a complete repair encoding indicates whether a repair to the currently identified cache is indicated or whether a new cache is targeted by the following repair.

Abstract: A WLAN (Wireless Local Area Network) transmission technique is provided where data is transmitted in two or more different transmission modes at different transmission rates. A transmission gain is determined to be applied when transmitting data. The transmission gain is determined to be transmission mode dependent such that the transmission gain in a first transmission mode is greater than the transmission gain in a second transmission mode if the transmission rate in the first transmission mode is lower than the transmission rate in the second transmission mode.

Abstract: A device is disclosed that comprises a passenger vehicle having a camera wirelessly communicating with a wireless router 121. The device communicates wirelessly to provide information using Internet Protocol (IP). The wireless connection is compliant with a standard, such as 802.11x, G3, G4, or 802.16x, and is part of a local area network. Image information is requested from and provided by the camera.

Abstract: A channel adapter includes a work queue entry table having entries configured for storing work queue entries awaiting respective acknowledgements. Each entry includes a work queue entry field for storing a corresponding work queue entry, and first and second link fields for respective linked lists. The channel adapter also includes a table manager configured for creating the linked lists, based on prescribed network conditions, for example for storage of a first list specifying a transmission order of the work queue entry fields and a second list specifying an acknowledgement order. Hence, the multiple link fields enable the work queue entry table to be shared for respective linked lists specifying respective attributes relative to the stored work queue entries.

Abstract: Methods for determining the square root, reciprocal square root, or reciprocal of a number performed by a processor of a computer system. The methods produce high precision estimates without using iterative steps. In addition, the methods taught herein utilize compressed tables for the coefficient terms A, B, and C from the quadratic expression Ax2+Bx+C, thus minimizing hardware requirements.