Abstract: A method of controlling write operations to a non-renamed register space includes receiving a write operation to a given register within the non-renamed register space. The method also includes determining whether a pending write operation to the given register exists. In response to determining that the pending write operation to the given register exists, the method includes blocking the write operation to the given register from being scheduled. However, in response to determining that the pending write operation to the given register does not exist, the method includes allowing the write operation to the given register to be scheduled. Further, if the pending write operation to the given register does not exist, the method includes allowing a subsequent write operation to a different register within the non-renamed register space to be scheduled.

Abstract: The claimed subject matter can provide a mechanism for ascertaining a variety of metrological data relating to one or more features (e.g., a transistor gate) of a chip/wafer. In addition, results of electrical testing on the chip/wafer can also be gathered and, together with the metrological data, input to a data store. From the information in the data store, a three-dimensional model for the feature(s) of the chip/wafer can be constructed and subjected to analysis, testing, and/or simulation. As well, the three-dimensional model can be optimized and an optimized three-dimensional model can be employed to affect process control in a feedback/forward manner, e.g., to apply optimizations to the next or the current wafer, respectively. Accordingly, the disclosed mechanisms may be used to optimize semiconductor performance, yield, or for research and development. In addition the three-dimensional model may be used in analysis, simulation, or debugging software.

Abstract: There is provided a method of making plurality of features in a first layer. A photoresist layer is formed over the first layer. Dense regions in the photoresist layer are exposed through a first mask under a first set of illumination conditions. Isolated regions in the photoresist layer are exposed through a second mask different from the first mask under a second set of illumination conditions different from the first set of illumination conditions. The exposed photoresist layer is patterned and then the first layer is patterned using the patterned photoresist layer as a mask.

Abstract: A method and apparatus are provided for a graded PECVD process that continuously modulates a set of flow and pressure conditions while the plasma power is turned on and a film is being deposited. A feedback mechanism specific to a give deposition recipe is used to generate, optimize and maintain a dynamic profile for a first input process parameter that produces a desired dynamic profile for a first output process parameter. An iterative approach produces a gradually converging series of dynamic profiles of an input profile parameter, which eventually succeeds in producing the desired dynamic profile for the first output process parameter of the graded PECVD process.

Abstract: An apparatus and method are disclosed for locking a table within a network switch. The table is used to store entries that contain addresses of network stations connected to the network switch. A scheduler regulates access to the address table by allocating prescribed time slots during which components of the network switch can access the address table. Each component requiring access to the address table must wait until it is assigned a time slot in order to further determine if any other components are accessing the address table. If none of the other components are accessing the address table, then the component requiring access can initiate a transaction.

Abstract: Products and/or services can be marketed in ways that allow configuration or selection of components, features or other attributes for which corresponding branding identities may be associated. In relation to such products, it has been discovered that consumers respond favorably to visually interconnected presentation of brands in which attributes of integration, optimization and/or coherence of a platform solution are suggested. Indeed, some visually interconnected presentations have been found to present a brand ecosystem in which the overall favorable impression of consumers is enhanced beyond that might otherwise be expected based on the individual brands or even the collection of individual brands when presented together, but without visual interconnection.

Abstract: Synchronization is attained between a source clock domain and a target clock domain of arbitrary frequency ratios and each of which periodically has edges nominally aligned to edges of a reference clock signal, marked by the assertion of a periodic sync signal. The periodic sync signal, synchronous with the source clock, is used to output to an unload pointer counter in the target clock domain the deassertion of a reset signal prior to the nominal alignment of the source clock and the target clock for sampling on the nominally aligned target clock edge. The deassertion of the reset signal is output to a load pointer in the source clock domain coincident with the nominally-aligned edges of the source clock and the target clock. Both loading and unloading start based on the reset deassertion being sampled on the nominally aligned edges in the appropriate clock domain.

Abstract: An antenna diversity method and a corresponding communication device are disclosed that may be used in wireless LAN receivers. An AGC (Automatic Gain Control) unit controls a gain when processing signals received from antennae. A periodical switching process is performed between at least two antennae. During this periodical switching process, signals from each of the antennae are received alternately. The gain obtained by processing each received signal by means of the AGC unit is monitored and the obtained gain is compared with a predetermined threshold value. When for one of the at least two antennae the gain is below the predetermined threshold value, the periodical switching process is stopped and the antenna used at the time when stopping the periodical switching process is selected. This technique may provide an improved antenna diversity of low complexity, high performance and a short settling time.

Abstract: A method of manufacturing an integrated circuit (IC) can utilize a shallow trench isolation (STI) technique. The shallow trench isolation technique can be used in an IC process. Separate liners for the trench are used for NMOS and PMOS regions. The liners can induce strain in the substrate.

Abstract: A semiconductor memory device may include an intergate dielectric layer of a high-K, high barrier height dielectric material interposed between a charge storage layer and a control gate. With this intergate high-K, high barrier height dielectric in place, the memory device may be efficiently erased using Fowler-Nordheim tunneling.

Abstract: A method for optimizing loop control of microcoded instructions includes identifying an instruction as a repetitive microcode instruction such as a move string instruction, for example, having a repeat prefix. The repetitive microcode instruction may include a loop of microcode instructions forming a microcode sequence. The microcode sequence is stored within a storage of a microcode unit. The method also includes storing a loop count value associated with the repetitive microcode instruction to a sequence control unit of the microcode unit. The method further includes determining a number of iterations to issue the microcode sequence for execution by an instruction pipeline based upon the loop count value. In response to receiving the repetitive microcode instruction, the method includes continuously issuing the microcode sequence for the number of iterations.

Abstract: A multi-ported register cell. The register cell includes a base cell and a plurality of history cells, each of which is coupled to the base cell. Each of the plurality history cells is coupled to write to the base cell through a first port, and each of the plurality of history cells is coupled to receive data from the base cell through a second port.

Abstract: An OFDM receiver is configured for suppressing pilot energy, and DC energy, from received I and Q components prior to estimating amplitude and phase imbalances of the received I and Q components. Hence, amplitude and phase imbalances can be estimated accurately despite channel fading and frequency variations between the transmitter and receiver.

Abstract: A method of planarizing a semiconductor device is provided. The semiconductor device includes a substrate, first and second components provided on the surface of the substrate, and a first material provided between and above the first and second components. The first component has a height greater than a height of the second component. The method includes performing a first polishing step on the semiconductor device to remove the first material above a top surface of the first component, to remove the first material above a top surface of the second component, and to level the top surface of the first component. The method also includes performing a second polishing step on the semiconductor device to planarize the top surfaces of the first and second components.

Abstract: A method of reducing critical dimensions of a feature in a anti-reflective coating layer structure can utilize a polymerizing agent. The anti-reflective coating structure can be utilized to form various integrated circuit structures. The anti-reflective coating can be utilized to form gate stacks comprised of polysilicon and a dielectric layer, conductive lines, or other IC structure. The polymerizing agent can include carbon, hydrogen and fluorine.

Abstract: A microprocessor may include one or more functional units configured to execute operations, a scheduler configured to issue operations to the functional units for execution, and at least one replay detection unit. The scheduler may be configured to maintain state information for each operation. Such state information may, among other things, indicate whether an associated operation has completed execution. The replay detection unit may be configured to detect that one of the operations in the scheduler should be replayed. If an instance of that operation is currently being executed by one of the functional units when operation is detected as needing to be replayed, the replay detection unit is configured to inhibit an update to the state information for that operation in response to execution of the in-flight instance of the operation. Various embodiments of computer systems may include such a microprocessor.

Abstract: A channel tracking module, configured for generating updated equalization coefficients for a frequency equalizer, is configured for determining a digital-based error value between equalized signals output by the frequency equalizer relative to predicted signals, for each subcarrier frequency of an OFDM symbol. The channel tracking module determines an accumulated error based on accumulating the digital-based error values for all the subcarrier frequencies of the OFDM symbol, for a prescribed successive number of OFDM symbols. The channel tracking module also determines a step size based on the accumulated error and relative to a prescribed step function configured for optimizing equalizer adjustments within stability limits. The channel tracking updates the equalization coefficients for each subscarrier frequency based on the accumulated error and the step size.

Abstract: A method is provided for fabricating a semiconductor on insulator (SOI) device. The method includes, in one embodiment, providing a monocrystalline silicon substrate having a monocrystalline silicon layer overlying the substrate and separated therefrom by a dielectric layer. A gate electrode material is deposited and patterned to form a gate electrode and a spacer. Impurity determining dopant ions are implanted into the monocrystalline silicon layer using the gate electrode as an ion implant mask to form spaced apart source and drain regions in the monocrystalline silicon layer and into the monocrystalline silicon substrate using the spacer as an ion implant mask to form spaced apart device regions in the monocrystalline substrate. Electrical contacts are then formed that contact the spaced apart device regions.

Abstract: A system including a single ended switching topology for high-speed bidirectional signaling includes a device coupled to a plurality of bidirectional signal paths. The device includes a plurality of voltage mode driver circuits, each coupled to a respective signal path. Each of the driver circuits may source a voltage when transmitting data and terminate a respective signal path to a ground reference when receiving data. The device also includes a shunt regulator circuit coupled to a voltage supply of the device. The shunt regulator may provide a current shunt from the voltage source to the ground reference in response to detecting a transition on the voltage supply in which the voltage increases above an average DC voltage.

Abstract: According to one exemplary embodiment, a method includes a step of forming a number of trenches in a dielectric layer, where the dielectric layer is situated over a wafer. The method further includes forming a metal layer over the dielectric layer and in the trenches such that the metal layer has a dome-shaped profile over the wafer. The method further includes performing a planarizing process to form a number of interconnect lines, where each of the interconnect lines is situated in one of the trenches. The dome-shaped profile of the metal layer causes the interconnect lines to have a reduced thickness variation across the wafer after performing the planarizing process. The interconnect lines are situated in an interconnect metal layer, where the dome-shaped profile of the metal layer causes the interconnect metal layer to have increased sheet resistivity uniformity across the wafer after performing the planarizing process.