Abstract: Disclosed herein are exemplary techniques for generating trace information streams to facilitate the reconstruction of the instruction execution history of a processing device for a given time period. The linear instruction pointers or other representations of the instructions executed by a processing device are output as a trace information stream. When one or more translation lookaside buffers (TLBs) used by the processing device are modified by the addition of a new linear-to-physical translation and/or the eviction of an old linear-to-physical translation, a representation of the newly added translation entry, or, alternatively the evicted translation entry, is inserted into the trace information stream. In this manner, the context for the address mapping of the instruction pointers of the trace information stream is provided and, consequently, the execution instruction history of the processing device may be more fully reconstructed.

Abstract: By providing a detailed hierarchical structure for an APC algorithm and by dynamically adapting a hierarchical level in this structure, an efficient utilization of controller data is ensured, while at the same time a large number of process conditions may be taken into consideration without requiring a re-design of the hierarchical structure.

Abstract: A method and a semiconductor device are provided in which respective contact layers having a specific intrinsic stress may be directly formed on respective metal silicide regions without undue metal silicide degradation during an etch process for removing an unwanted portion of an initially deposited contact layer. Moreover, due to the inventive concept, the strain-inducing contact layers may be formed directly on the respective substantially L-shaped spacer elements, thereby enhancing even more the stress transfer mechanism.

Abstract: A method includes forming a group of disposable hard mask structures on a semiconductor device that includes a group of memory cells. The method further includes using the disposable hard mask structures to precisely control a junction profile of the memory cells.

Abstract: A semiconductor structure comprises a transistor element formed in a substrate. A stressed layer is formed over the transistor element. The stressed layer has a predetermined compressive intrinsic stress having an absolute value of about 1 GPa or more. Due to this high intrinsic stress, the stressed layer exerts considerable elastic forces to the channel region of the transistor element. Thus, compressive stress is created in the channel region. The compressive stress leads to an increase of the mobility of holes in the channel region.

Abstract: Semiconductor devices including logic circuitry and embedded memories may be tested using one or more flip-flops in a scan chain that are connected to a control input of an MBIST logic, thereby allowing the control of the MBIST logic during a simultaneous scan test and memory test run. By combining the output of the MBIST logic with the output of the scan chain, fault diagnosis is maintained.

Abstract: A method includes providing a process controller for controlling a process tool. The process tool is controlled in accordance with a process parameter. Measurements associated with the processing parameter for a plurality of runs of the process tool are accessed. A performance measure for the process controller is generated based on the process parameter and the measurements. A system includes a process tool, a process controller, and a performance monitor. The process controller is configured to control the process tool in accordance with a process parameter. The performance monitor is configured to retrieve measurements associated with the processing parameter for a plurality of runs of the process tool and generate a performance measure for the process controller based on the measured processing parameters.

Abstract: The present invention makes it possible to precisely deposit a material adjacent a feature on a substrate. A layer of the material is deposited on the substrate. The layer is planarized and exposed to an etchant. The etchant is adapted to selectively remove the material. The exposing of the layer to the etchant is stopped prior to a complete removal of the layer.

Abstract: A method for efficiently and accurately measuring a maximum Vcc calculation or failure rate and lifetime projection for microprocessors and other semiconductor products analytically scales low voltages applied to thinner oxides to thicker oxides. The expanded voltage window that is closer to the use voltage is obtained thereby to provide accurate voltage acceleration factors and max Vce extraction.

Abstract: Instructions involving a relatively significant information transfer or a particular type of information transfer via a cache, or specified address ranges within cache causing a cache miss result in the application of a restricted access policy to control access to one or more partitions of the cache so as to reduce or prevent the overwriting of information that is expected to be subsequently used by the cache or by a processor. A processor or other system component may assert a signal which is utilized to select between one or more access policies based on instructions or their type so that an access may be applied to control access to one or more ways of the cache during the information transfer operation associated with the instruction. Similarly, a cache way select module may select between one or more access policies based on an address range so that an access policy may be applied to control access to one or more ways of the cache during access to a specific range of memory.

Abstract: A cache is configured to have a first cache line allocation policy for a memory address. An instruction associated with the memory address is received and a second cache line allocation policy is determined based on the instruction. The cache is reconfigured to have the second cache line allocation policy in response to receiving the instruction. A data processor includes processor core to receive and execute an instruction associated with a memory address, a cache including a plurality of cache lines, and a cache allocation module to determine a cache line allocation policy based on the instruction and to reconfigure the cache to have the cache line allocation policy for execution of the instruction at the processor core.

Abstract: The present invention provides a technique for estimating critical dimensions of highly scaled circuit features on the basis of scanning electron microscopy, wherein area fractions of a scan area are determined. Preferably, the SEM is operated with high electron beam energies to enhance the overall resolution and to reduce edge effects and image artifacts. Thus, fast and statistically significant measurement results may be obtained, thereby allowing enhanced process control.

Abstract: A method for manufacturing a memory device having a metal nanocrystal charge storage structure. A substrate is provided and a first layer of dielectric material is grown on the substrate. An absorption layer is formed on the first layer of dielectric material. The absorption layer includes a plurality of titanium atoms bonded to the first layer of dielectric material, a nitrogen atom bonded to each titanium atom, and at least one ligand bonded to the nitrogen atom. The at least one ligand is removed from the nitrogen atoms to form nucleation centers. A metal such as tungsten is bonded to the nucleation centers to form metallic islands. A dielectric material is formed on the nucleation centers and annealed to form a nanocrystal layer. A control oxide is formed over the nanocrystal layer and a gate electrode is formed on the control oxide.

Abstract: A system includes a process tool for processing a workpiece, a process controller, and a fault monitor. The process controller is configured to determine a control action for updating an operating recipe of the process tool. The fault monitor is configured to determine at least one fault detection threshold based on the control action. A method includes determining a control action for updating an operating recipe of a process tool and determining at least one fault detection threshold based on the control action.

Abstract: The present invention provides a method and apparatus for determining a root cause of a fault. The method includes detecting at least one fault associated with at least one first wafer processed according to a first processing context and processing at least one second wafer according to at least one second processing context. The second processing context is different than the first processing context. The method also includes determining a root cause associated with the fault based on the first processed wafer and the second processed wafer.

Abstract: A method and apparatus for scheduling ahead in a process flow for a manufacturing domain entity are disclosed. The method includes detecting an occurrence of a triggering event defined for a current process operation on the manufacturing domain entity; and scheduling the target process operation upon expiration of a timed offset from the detection of the triggering event responsive to the detection thereof, the timed offset being defined for the target process operation scheduling. In various aspects, the apparatus includes a program storage medium encoded with instructions that, when executed by a computing device, perform such a method and a computer programmed to perform such a method. In still other aspects, the apparatus includes a process flow implementing such a method.

Abstract: In one illustrative embodiment, the method comprises providing an SOI substrate comprised of an active layer, a buried insulation layer and a bulk substrate, forming a doped region in the bulk substrate under the active layer, forming a plurality of transistors above the SOI substrate in an area above the doped region and applying a voltage to the doped region to vary a threshold voltage of at least one of the plurality of transistors.

Abstract: A data processor (300) is adapted for use in a non uniform memory access (NUMA) data processing system (10) having a local memory (320) and a remote memory. The data processor (300) includes a central processing unit (302) and a communication link controller (310). The central processing unit (302) executes a plurality of instructions including an atomic instruction on a lock variable, and generates an access request that includes a lock acquire attribute in response to executing the atomic instruction on the lock variable. The communication link controller (310) is coupled to the central processing unit (302) and has an output adapted to be coupled to the remote memory, and selectively provides the access request with the lock acquire attribute to the remote memory if an address of the access request corresponds to the remote memory.

Abstract: A system for optimizing critical dimension uniformity in semiconductor manufacturing processes is provided. The system comprises a bake plate simulator to model a physical bake plate. A finite element analysis engine uses information from the bake plate simulator to calculate missing information. A lithography simulator predicts outcomes of a lithography process using information from the bake plate simulator and the finite element analysis engine. The system can be used in a predictive capacity or as part of a process control system.

Abstract: Different types of crystalline semiconductor regions are provided on a single substrate by forming a dielectric region within a first crystalline semiconductor region. Thereafter, a second crystalline region is positioned above the dielectric region by wafer bond techniques. In preferred embodiments, isolation structures may be formed in the first crystalline region along with the dielectric region. In particular, crystalline semiconductor regions of different crystallographic orientations may be formed, wherein a high degree of flexibility and compatibility with currently used CMOS processes is maintained.