Abstract: The disclosure provides methods to mitigate and/or eliminate problems associated with removal of carbon-based resists from organic low k dielectrics. The methods include forming an organic low k dielectric layer over a semiconductor substrate, forming a capping layer over the organic low k dielectric layer, forming a silicon-containing resist over the capping layer, patterning the silicon-containing resist layer to expose portions of the capping layer and to form a patterned silicon oxide layer, removing the organic low k dielectric layer to form one or more openings, and removing the patterned silicon oxide layer. The silicon-containing resist facilitates efficient patterning of the organic low k-dielectric layers, and thereby increases the performance and cost-effectiveness of semiconductor devices fabricated using organic low k dielectrics.

Abstract: A device and method is illustrated to prefetch information based on a location of an instruction that resulted in a cache miss during its execution. The prefetch information to be accessed is determined based on previous and current cache miss information. For example, information based on previous cache misses is stored at data records as prefetch information. This prefetch information includes location information based on an instruction that caused a previous cache miss, and is accessed to generate prefetch requests for a current cache miss. The prefetch information is updated based on current cache miss information.

Abstract: Described herein are systems and methods that reduce the latency which may occur when a level one (L1) cache issues a request to a level two (L2) cache, and that ensure that a translation requests sent to an L2 cache are flushed during a context switch. Such a system may include a work queue and a cache (such as an L2 cache). The work queue comprises a plurality of state machines, each configured to store a request for access to memory. The state machines can monitor requests that are stored in the other state machines and requests that the other state machines issue to the cache. A state machine only sends its request to the cache if another state machine is not already awaiting translation data relating to the that request. In this way, the request/translation traffic between the work queue and the cache can be significantly reduced.

Abstract: A serial link system is provided for determining a worst-case cumulative data eye. The system includes a transmitter, a receiver, and a channel between the transmitter and receiver such that data sent by the transmitter is received by the receiver through the channel. The channel includes a plurality of connections including a victim and at least first and second aggressors, with the victim being disposed between the first and second aggressors. The system also includes a controller constructed and arranged to determine a worst case cumulative data eye based on a data pattern of the victim, jitter on the victim, an effect a data and jitter pattern on the first aggressor has on the victim and an effect a data and jitter pattern of the second aggressor has on the victim and to combine the effects of the data pattern of the victim, the jitter on the victim and the effects of the first and second aggressors on the victim into a single pattern to determine cumulative data eye for use in a simulator.

Abstract: Computer system configuration resources include first and second control circuits in respective first and second integrated circuits. A communication link, which transfers data over a plurality of logical pipes, connects the two integrated circuits. Configuration of the link utilizes a link bridge that includes upstream (located closest to the CPU) configuration registers that are within the first control circuit and downstream ((located farthest from the CPU) configuration registers within the second control circuit. A link header, which includes upstream data for the first control circuit and down stream data for the second control circuit, is used to initialize the link. The upstream and downstream data may include information specifying the size of the communication link.

Abstract: During the formation of an underfill material provided between a carrier substrate and a semiconductor chip, a common motion of particles contained in the underfill material is initiated towards the semiconductor chip, thereby adjusting the thermal and mechanical behavior of the underfill material. For instance, by applying an external force, such as gravity, a depletion zone with respect to the filler particles may be created in the vicinity of the carrier substrate, while a high particle concentration may be obtained in the vicinity of the semiconductor chip. Hence, thermal and mechanical stress redistribution by means of the underfill material may be enhanced.

Abstract: A method of forming a dielectric between memory cells in a device includes forming multiple memory cells, where a gap is formed between each of the multiple memory cells. The method further includes performing a high density plasma deposition (HDP) process to fill at least a portion of the gap between each of the multiple memory cells with a dielectric material.

Abstract: Methods of making memory devices/cells are disclosed. A memory cell contains first and second electrode layers and a controllably conductive media therebetween. The controllably conductive media contains a copper sulfide-containing passive layer and active layer containing a Cu-doped tantalum oxide and/or titanium oxide layer. Methods of using the memory devices/cells, and devices such as computers containing the memory devices/cells are also disclosed.

Abstract: A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.

Abstract: A method of forming an abrupt junction device with a semiconductor substrate is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed on the semiconductor substrate adjacent the gate and the gate dielectric. A thickening layer is formed by selective epitaxial growth on the semiconductor substrate adjacent the sidewall spacer. Raised source/drain dopant implanted regions are formed in at least a portion of the thickening layer. Silicide layers are formed in at least a portion of the raised source/drain dopant implanted regions to form source/drain regions, beneath the silicide layers, that are enriched with dopant from the silicide layers. A dielectric layer is deposited over the silicide layers, and contacts are then formed in the dielectric layer to the silicide layers.

Abstract: According to the present invention, a wet chemical oxidation and etch process cycle allows efficient removal of contaminated silicon surface layers prior to the epitaxial growth of raised source and drain regions, thereby effectively reducing the total thermal budget in manufacturing sophisticated field effect transistor elements. The etch recipes used enable a controlled removal of material, wherein other device components are not unduly degraded by the oxidation and etch process.

Abstract: The present application describes a system and method of profiling a computer system based on a profiling state machine. The profiling state machine defines various states in which the system data can be collected for a particular application. The state machine allows system data collection regardless of timing intervals or event counters. When a state is identified for system data collection, the profiler application collects system data for the user. A profiling application driver monitors the state machine and manages the data collection based on the state machine. The profiling application driver controls the profiling configurations thus allowing a correlated data collection for timing intervals and event counter.

Abstract: A method and apparatus is provided for processing tasks with failure recovery. The method includes storing one or more tasks in a queue, wherein each task has an associated exit routine, and determining at least one task to process based on a priority scheme. The method further includes processing the at least one task, and calling the exit routine based on determining that the task has not completed processing within a preselected period of time.

Abstract: A flip-flop circuit includes a differential stage coupled to a latch stage. The differential stage comprises cross-coupled dynamic logic and only provides a single output to the latch stage. During an evaluation phase, the state of a data input signal is sensed. Depending upon the state of the data input signal, either an output side or reference side of the differential stage is discharged. Also, during the evaluation phase, the latch stage write port is enabled while feedback is disabled, and the flip flop thereby samples and stores an output signal from the output side of the differential stage. Upon initiation of the next precharge phase, the latch stage write port is disabled and feedback is enabled, thereby retaining its present state. Only a single side of the differential stage is used to drive the latch stage and the differential stage may be implemented in an asymmetric fashion.

Abstract: A device that receives data transmitted over a network medium includes a memory that stores phase information associated with a pilot tone. The device also includes logic that identifies a second pilot tone received with a number of tones and determines the phase of the second pilot tone. The logic also determines a difference between the phases of the two pilot tones and modifies phase information associated with a number of tones based on the difference. The received data with the modified phase information may then be decoded.

Abstract: A method of manufacturing a memory device includes forming a first dielectric layer over a substrate and forming a charge storage element over the first dielectric layer. The method also includes forming a second dielectric layer over the charge storage element and forming a control gate over the second dielectric layer. The method further includes depositing an interlayer dielectric over the control gate at a high temperature.

Abstract: The present invention provides a method and apparatus for detecting step and impulse disturbances. The method includes determining a pattern based on a plurality of probabilities associated with a corresponding plurality of wafer processing parameters and determining a type of a disturbance based upon the pattern.

Abstract: A method of doping fins of a semiconductor device that includes a substrate includes forming multiple fin structures on the substrate, each of the fin structures including a cap formed on a fin. The method further includes performing a first tilt angle implant process to dope a first pair of the multiple fin structures with n-type impurities and performing a second tilt angle implant process to dope a second pair of the multiple fin structures with p-type impurities.

Abstract: Methods for fabricating devices having small feature sizes are provided. In an exemplary embodiment, a method comprises forming a patterned first mask layer overlying a subject material layer and isotropically etching the patterned first mask layer. A second masking layer is deposited overlying the patterned first mask layer and the isotropically-etched patterned first mask layer is exposed. The isotropically-etched patterned first mask layer is removed and the subject material layer is etched to form a feature therein.

Abstract: An integrated circuit with a semiconductor substrate is provided. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. A silicide layer is on the semiconductor substrate adjacent the gate and the gate dielectric. The silicide layer incorporates a substantially uniformly distributed and concentrated dopant therein. A shallow source/drain junction is beneath the salicide layer. An interlayer dielectric is above the semiconductor substrate, and contacts are in the interlayer dielectric to the salicide layer.