Abstract: A baseboard management controller (BMC) hosts a real-time clock and non-volatile RAM replacement that does not require a battery power supply. The BMC includes an I/O mapped interface responsive to I/O accesses to an address range associated with storage locations of a real-time clock circuit and storage locations holding configuration information. The BMC receives power when a processor coupled to the BMC is not powered. The I/O address range may include 70h and 71h. A network interface may communicate information between a network external to the BMC and the real-time clock and/or the storage locations holding the configuration information. The network external to the BMC may communicate clock synchronization and/or configuration information to the BMC.

Abstract: A method for delayed memory access request arbitration includes dispatching a first memory access request to a memory controller and dispatching a second memory access request to the memory controller in response to an anticipated completion of a memory access operation represented by the first memory access request. Another method includes receiving a first memory access request at a bus interface unit at a first time, dispatching a second memory access request to a memory controller at a second time subsequent to the first time, receiving a third memory access request at the bus interface unit at a third time subsequent to the second time, dispatching the third memory access request to the memory controller at a fourth time subsequent to the third time and dispatching the first memory access request to the memory controller at a fifth time subsequent to the fourth time.

Abstract: In a personal Internet communication device, an optimized operating system image (NK.bin) is constructed from the operating system component files required to provide a minimum threshold of operating system functionality. By reducing the size of the operating system image, the time required to load the operating system is reduced.

Abstract: A receiving unit in a communication system for receiving a communication signal. The receiving unit is preferably a wireless local area network (WLAN) receiver. The receiving unit comprises a synchronization data detection section and a frequency error correction section. The synchronization data detection section detects predefined synchronization data included in the received communication signal and computes an initial estimate of a frequency error of the received communication signal. The frequency error correction section corrects the frequency of the received communication signal based on frequency error estimates. An initial frequency error estimate used for a first frequency error correction is received from said synchronization data detection.

Abstract: A system and method for converting information stored on a magnetic medium to DVD format. A tape transport mechanism may sample information stored on a magnetic medium at a selected rate where the selected rate is correlated to an available buffer size in a data processing system. The rate at which information is sampled may be less than the NTSC standard of 30 frames/second thereby requiring less storage to store the digital video representation. The sampled information may be captured and converted into a digital format. The digitized magnetic waveform may be transferred to the data processing system configured to convert the digitized magnetic signals into digitized television waveforms to recover the analog and video content. The digitized television waveforms may then be converted into a digital video representation. The digitized information may then be temporarily stored in the available buffer prior to being compressed and converted into DVD format.

Abstract: An integrated circuit, a client computer system, and a method for operating the integrated circuit in the client computer system. The integrated circuit includes a first bus interface logic for coupling to a first external bus, a microcontroller configured as an Alert Standard Format management engine, and a watchdog timer coupled to the microcontroller. The microcontroller is further configured to receive Alert Standard Format sensor data over the first external bus. The watchdog timer is coupled to receive a reset input upon a predetermined change in a system state. The watchdog timer is further configured to provide an indication to the microcontroller in response to an expiration of the watchdog timer.

Abstract: A method and system for providing a halo implant to a semiconductor device is disclosed. The method and system includes providing a thin photoresist layer that covers a substantial amount of an active area including a source region and a drain region of the semiconductor device. The method and system further includes providing the halo implant to the semiconductor device, using the thin photoresist layer as a mask. Utilizing this thin photoresist layer, taking into account other height variables, the source and drain regions can be opened only as needed. At a 45° angle, the implant can be delivered to all transistors in the circuit in the targeted area as well as getting only a large amount of the dose (up to ¾ of the dose) to the transistor edge which sits on the trench edge.

Abstract: A method of producing design rules including generating a plurality of parametrically varying geometric layouts and simulating how each geometric layout will pattern on a wafer. Edges of structures within the simulated geometric layouts can be classified based on manufacturability and design rules can be created to disallow layouts demonstrating poor manufacturability.

Abstract: A host controller such as a USB host controller in a southbridge, and a corresponding operation method are provided. The host controller comprises a descriptor fetch unit that is adapted to send out requests for descriptors and receive descriptors in reply to the requests. The descriptors are data structures for describing attributes of the data transfer to and from the devices controlled by the host controller. The host controller further comprises a descriptor cache that is adapted to store prefetched descriptors. The descriptor cache is further adapted to store individual replacement control values for at least a part of the stored prefetched descriptors. The host controller is arranged to replace a stored prefetched descriptor in the descriptor cache by a newly prefetched descriptor based on the replacement control value that is associated with the stored prefetched descriptor. The replacement technique may improve the overall efficiency of the host controller operation.

Abstract: By heat treating a silicon dioxide liner prior to patterning a silicon nitride spacer layer, the etch selectivity of the silicon dioxide with respect to the silicon nitride is increased, thereby reducing or eliminating the problem of pitting through the silicon dioxide layer. This allows further scaling of the devices, wherein an extremely thin silicon dioxide liner is required to obtain an accurate lateral patterning of the dopant profile in the drain and source regions.

Abstract: A method includes storing data associated with a plurality of reticles. Reticle history information is received. The reticle history information is linked to a selected reticle. The linked reticle history information is stored. A reticle information system includes a reticle database and a loader. The reticle database is operable to store data associated with a plurality of reticles. The loader is operable to receive reticle history information, link the reticle history information to a selected reticle, and store the linked reticle history information in the reticle database.

Abstract: The present invention provides a method and apparatus for using a video port, such as a display data channel (DDC) port, in two modes for transmitting and receiving serial data streams. In one mode, the DDC port is used to control the operation of a video display of an information processing system, such as a personal internet communicator (PIC). In another mode, the DDC channel is used as a serial port for accessing the PIC system for diagnostic and configuration purposes.

Abstract: A phase error correction technique in receivers such as WLAN receivers is provided. Such receivers comprise a phase error correction unit connected to receive an input signal having a phase error and adapted to generate an output signal having a corrected phase error. Further, the receiver comprises a despreader which is adapted to despread a data signal. The despreader is connected to the phase error correction unit to provide the despread data signal to the phase error correction unit. The phase error correction unit is arranged for correcting the phase error dependent on the despread data signal. The despreader may be a Barker matched filter or a CCK matched filter, and there may be provided a multiplexer for selecting one of the filters.

Abstract: A method for verifying operation of a media acceleration engine. The method includes providing input data to a replica of a media acceleration engine wherein the input data including a complete set of media streams, processing the input data via the replica of the media acceleration engine to provide replica output data, providing a subset of the complete set of media streams to a design of the media acceleration engine, simulating the operation of the design of the media acceleration engine using the subset of the complete set of media streams to provide design output data, comparing the replica output data with respective design output data, and verifying the operation of the media acceleration engine when replica output data matches corresponding design output data.

Abstract: A timing error correction technique for use in data communications receivers such as WLAN (Wireless Local Area Network) receivers is provided where an input signal is received that has a timing error, the timing error is corrected, and a signal having a corrected timing error is output. The timing error correction comprises performing an early-late correlation on the signal that has the corrected timing error. The early-late correlation comprises the generation of at least one early and late sample pair, the generation of an error signal that is indicative of the difference between the early and late samples, and the generation of at least one control signal based on the error signal. A time offset correction algorithm is performed dependent on the control signal.

Abstract: A system device receives a first data signal and a first strobe signal from a dual-data-rate (DDR) memory. A first delay value representative of a delay to a predetermined phase location of the first strobe signal is determined. The first delay is adjusted based on a first offset value to generate a first adjusted delay value used to delay the first strobe signal. A first edge of a first pulse of the first delayed strobe signal is used to latch a first data value of the first data signal.

Abstract: A technique for performing a frequency error correction process is provided that may be used in receivers of wireless local area network systems. The technique comprises a three-phase process generating a frequency approximation value based on a frequency error estimate, starting a channel estimation process that uses the generated frequency approximation value, refining the generated frequency approximation value, and compensating a frequency error using the refined frequency approximation value. Further, a corresponding integrated circuit chip and an operation method are provided. Using the technique for performing a frequency error correction process may provide high reliability, high precision and improved operation speed.

Abstract: An average tracking mechanism for a data communication receiver is provided. The average tracking mechanism of the receiver is connected to receive an input stream of data samples and is adapted to keep track of an average over a predefined number of most recently received data samples. The average tracking mechanism comprises a calculation unit that is adapted to calculate an approximate value of the average and a storage unit for storing calculated approximate values. The calculation unit is adapted to calculate the approximate value by retrieving a previously calculated approximate value from the storage unit and calculating a weighted sum of the retrieved approximate value and a current data sample. The average approximation technique may be used in a comb filter of a preamble detector in a WLAN receiver.

Abstract: An integrated circuit device provides an operational set point indicator. The operational set point indicator is utilized for obtaining a plurality of operational set points. Each of the plurality of operational set points can be a pair of an operational voltage and an operational frequency for application to the integrated circuit device. The operational set point indicator can be, for example, a Schmoo Class Register, a Device Identification Register, or actual operating condition information of the integrated circuit device. The Schmoo Class Register and the Device Identification Register are utilized to identify a performance state table in memory. The actual operating conditional information can be one or more entire Schmoo Plots for the device or a subset of such information. Operational set points are used during operation of the integrated circuit device, for example, in power management applications.

Abstract: It has been discovered that all causes of critical dimension variation, both known and unknown, are compensated by adjusting the time of photoresist etch. Accordingly, a control method employs a control system using photoresist etch time as a manipulated variable in either a feedforward or a feedback control configuration to control critical dimension variation during semiconductor fabrication. By controlling critical dimensions through the adjustment of photoresist etch time, many advantages are achieved including a reduced lot-to-lot variation, an increased yield, and increased speed of the fabricated circuits. In one embodiment these advantages are achieved for polysilicon gate critical dimension control in microprocessor circuits. Polysilicon gate linewidth variability is reduced using a control method using either feedforward and feedback or feedback alone. In some embodiments, feedback control is implemented for controlling critical dimensions using photoresist each time as a manipulated variable.