Abstract: A method and apparatus utilizing a single processor and a plurality of memories for providing audio synchronization including writing an incoming PES audio stream having header information, PTS timing information and payload information and audio information to an input buffer. The method and apparatus further includes reading the incoming audio stream from the input buffer and parsing the timing information and the audio information. The audio information, ES information, is written to an intermediate buffer. Based on the timing information, the method and apparatus further includes reading the audio information from the intermediate buffer and decoding the audio information to generate decoded audio information, PCM information. The method and apparatus includes writing the decoded audio information in an output buffer, wherein the decoded audio information may be provided from the output buffer to a digital-to-analog converter and thereupon provided to an audio system.

Abstract: A method of forming a memory device includes forming a memory stack on a substrate. The memory stack includes an alumina layer acting as an intergate dielectric layer. A transistor is formed on the substrate in an area separate from the memory stack. The transistor is formed to include thin gate oxide via a dry oxidation technique and a gate layer on the thin gate oxide. The thin gate oxide is formed without subjecting the thin gate oxide to thermal annealing with N2O.

Abstract: A fully depleted SOI MOSFET arrangement includes a buried oxide (BOX) layer with recesses in the BOX layer and a post extended upwardly between the recesses. A thin channel region is formed on the post and a gate over the channel. Deep source/drain region are adjacent to the channel region and extend into the recesses.

Abstract: Silicon-on-insulator (SOI) structures with silicon layers less than 20 nm in thickness are used to form extremely thin silicon-on-insulator (ETSOI) semiconductor devices. ETSOI semiconductor devices can be efficiently manufactured by mesa isolation techniques. A method of forming a plurality of semiconductor devices is provided comprising a SOI structure. The SOI structure comprises a substrate, an insulating layer overlying the substrate, and a silicon layer overlying the insulating layer, wherein the silicon layer has a thickness less than 20 nm. The silicon layer is patterned to create at least two laterally spaced apart silicon layers. A semiconductor device is formed at each of the at least two laterally spaced apart silicon layers.

Abstract: A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).

Abstract: A method is provided for manufacturing, the method including processing a workpiece in a processing step, measuring a parameter characteristic of the processing performed on the workpiece in the processing step, and forming an output signal corresponding to the characteristic parameter measured. The method also includes setting a target value for the processing performed in the processing step based on the output signal.

Abstract: For clamping a reticle within a lithography system, a first area in the center of the reticle is clamped to a chuck of the lithography system at a first time point. In addition, a second area toward an outer perimeter of the reticle is clamped to the chuck at a second time point after the first time point such that the reticle is flattened against the chuck. With such flattening of the reticle, image placement error on a semiconductor substrate is minimized.

Abstract: A method and apparatus is provided for fault notification based on a severity level. The method comprises detecting a fault associated with a processing tool that is adapted to process one or more workpieces, determining a fault severity level of the detected fault and selecting at least one user to notify of the fault based on the severity level of the fault.

Abstract: A monitoring system is presented. The monitoring system may include a first chemical vessel containing a first chemical mixture and a second chemical vessel containing a second chemical mixture. The monitoring system may further include a sensor configured to selectively receive a first sample flow of the first chemical mixture from the first chemical vessel and a second sample flow of the second chemical mixture from the second chemical vessel. The sensor may be configured to measure a first sample attribute value of the first sample flow and a second sample attribute value of the second sample flow. By multiplexing multiple sample flows through a sensor, the monitoring system may monitor attributes of multiple chemical mixtures without requiring separate sensors for each chemical mixture monitored by the system. In an embodiment, the monitoring system is preferably configured to control an attribute of a chemical mixture.

Abstract: In a system and a method according to the present invention, a seismic signal from a seismic sensor coupled to a drive assembly of a pad conditioning system is used to estimate the status of one or more consumables in a CMP system.

Abstract: The present invention relates to a method of run-to-run control of a manufacturing process. A plurality of runs of the manufacturing process is performed. In each of the runs, a value of a process input is applied to the manufacturing process. A measured value of a process output of the respective run is determined. A process input quantity is calculated based on the measured value, the applied process input, a target value of the process output and at least one value of a sensitivity parameter. The sensitivity parameter describes a variation of the process output caused by a variation of the process input. The process input applied in a subsequent one of the plurality of runs is based on the process input quantity. The sensitivity parameter is modified between at least one pair of the runs of the manufacturing process.

Abstract: A method for identifying faults in a semiconductor fabrication process includes storing measurements for a plurality of parameters of a wafer in the semiconductor fabrication process. A first subset of the parameters is selected. The subset is associated with a feature formed on the wafer. A principal component analysis model is applied to the first subset to generate a performance metric. A fault condition with the wafer is identified based on the performance metric. A system includes a data store and a fault monitor. The data store is adapted to store measurements for a plurality of parameters of a wafer in a semiconductor fabrication process. The fault monitor is adapted to select a first subset of the parameters, the subset being associated with a feature formed on the wafer, apply a principal component analysis model to the first subset to generate a performance metric, and identify a fault condition with the wafer based on the performance metric.

Abstract: The present invention provides a method and apparatus for dynamic adjustment of an active sensor list. The method includes providing an active sensor list indicative of at least one sensor associated with at least one processing tool, the at least one sensor being communicatively coupled to a network having an associated bandwidth, receiving information indicative of a state of at least one of the processing tools, and modifying the active sensor list based on the information indicative of the state of the at least one of the processing tools and the associated network bandwidth.

Abstract: A method for analyzing a semiconductor device tests a semiconductor device to produce first and second data. A clustering method is applied to the first data, creating a clustered first data. The clustered first data is then correlated with the second data to determine analyzed data.

Abstract: A method and system for changing the executable status of an operation following a branch misprediction. In one embodiment, a method may include predicting an execution path of a first conditional branch operation stored in an entry of a trace cache, and in response to predicting the execution path, if a first operation stored in the entry of the trace cache is not in the execution path according to the prediction, assigning to the first operation a non-executable status indicative that the first operation is not in the execution path. The method may further include detecting that the prediction is incorrect subsequent to assigning the non-executable status to the first operation and assigning an executable status to the first operation in response to detecting the incorrect prediction, where the executable status is indicative that the first operation is in the execution path.

Abstract: A light reflected from a semiconductor die is used for enhanced control of substrate removal from the die. According to an example embodiment of the present invention, light reflected from a semiconductor die as it is undergoing substrate removal is used to detect the progress of the substrate removal process, and the removal process is controlled therefrom. In different embodiments, the reflected light is used to detect the removal of a portion of a layer of material in the die and to detect the removal of an entire layer of material.

Abstract: A semiconductor device includes a substrate and an insulating layer on the substrate. The semiconductor device also includes a fin structure formed on the insulating layer, where the fin structure includes first and second side surfaces, a dielectric layer formed on the first and second side surfaces of the fin structure, a first gate electrode formed adjacent the dielectric layer on the first side surface of the fin structure, a second gate electrode formed adjacent the dielectric layer on the second side surface of the fin structure, and a doped structure formed on an upper surface of the fin structure in the channel region of the semiconductor device.

Abstract: A mechanism has been developed by which the impact on speed from back end-of-line interconnect layers may be characterized. A method for designing interconnect layers of an integrated circuit includes coupling a capacitive load to a speed sensing circuit to measure a delay corresponding to an interconnect structure of an integrated circuit design, selectively configuring the capacitive load by selectively coupling at least one of a plurality of capacitive structures, the capacitive structures including at least a portion of a plurality of metal layers. The capacitive load is representative of the interconnect structure. The method includes measuring the delay corresponding to the capacitive load to characterize at least one layer of the interconnect structure. In some realizations, the method also includes characterizing the interconnect structure based at least in part on the delay measurement.

Abstract: A front-end-of-line piece of a semiconductor die is manufactured in a first manufacturing line. A back-end-of-line piece of a semiconductor die is manufactured using a second manufacturing line, which will typically be different than the first manufacturing line. The front-end-of-line piece and the back-end-of-line piece are combined during a joining process to form a semiconductor die. The semiconductor die is subsequently tested to determine if the semiconductor die is a functional semiconductor die.

Abstract: A communications system includes a physical layer hardware unit and a processing unit. The physical layer hardware unit is adapted to communicate data over a communications channel. The physical layer hardware unit is adapted to receive unencrypted control codes and encrypted user data over the communications channel and transmit an upstream data signal over the communications channel based on the control codes. The processing unit is adapted to execute a software driver for interfacing with the physical layer hardware unit. The software driver includes program instructions for implementing a protocol layer to decrypt the user data and provide the upstream data to the physical layer hardware unit. A method for configuring a transceiver includes receiving unencrypted control codes over a communications channel; receiving encrypted user data over the communications channel; and transmitting an upstream signal over the communications channel based on transmission assignments defined by the control codes.