Patents Assigned to Advanced Semiconductor Engineering
  • Publication number: 20210225917
    Abstract: An optical module includes an image sensor and micro lens array. The image sensor has at least one group of pixels. The micro lens array is disposed on the image sensor. The at least one group of pixels is shifted from the micro lens array in a first direction from a top view perspective.
    Type: Application
    Filed: January 16, 2020
    Publication date: July 22, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Hsin-Ying HO
  • Publication number: 20210226317
    Abstract: A semiconductor device package is provided that includes a substrate, a first support structure disposed on the substrate and a first antenna. The first support structure includes a first surface spaced apart from the substrate by a first distance. The first antenna is disposed above the first surface of the first support structure.
    Type: Application
    Filed: April 5, 2021
    Publication date: July 22, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Guo-Cheng LIAO, Yi Chuan DING
  • Publication number: 20210225737
    Abstract: A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a first semiconductor element, a first redistribution layer, a second redistribution layer, and a conductive via. The first semiconductor element has a first active surface and a first back surface opposite to the first active surface. The first redistribution layer is disposed adjacent to the first back surface of the first semiconductor element. The second redistribution layer is disposed adjacent to the first active surface of the first semiconductor element. The conductive via is disposed between the first redistribution layer and the second redistribution layer, where the conductive via inclines inwardly from the second redistribution layer to the first redistribution layer.
    Type: Application
    Filed: January 21, 2020
    Publication date: July 22, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Hsu-Nan FANG
  • Publication number: 20210225742
    Abstract: Present disclosure provides a lead frame, including a die paddle and a plurality of leads surrounding the die paddle. Each of the leads including a finger portion proximal to the die paddle and a lead portion distal from the die paddle. The finger portion includes a main body and at least one support structure. The respective support structures on adjacent leads are mutually isolated, and a distance between the support structure and the die paddle is smaller than a distance between the lead portion and the die paddle. A semiconductor package structure including the lead frame described herein and a semiconductor package assembly including the semiconductor package structure described herein are also provided.
    Type: Application
    Filed: January 22, 2020
    Publication date: July 22, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jyun-Chi JHAN, Guo-Cheng LIAO
  • Publication number: 20210225747
    Abstract: A semiconductor device package includes a carrier, an electronic component and a connector. The electronic component is disposed on the carrier. The connector is disposed on the carrier and electrically connected to the electronic component. A S11 parameter of the connector is less than ?20 dB.
    Type: Application
    Filed: January 22, 2020
    Publication date: July 22, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuanhao YU, Cheng Yuan CHEN, Chun Chen CHEN, Jiming LI, Chien-Wen TU
  • Publication number: 20210225781
    Abstract: Present disclosure provides a semiconductor package structure, which includes a redistribution layer (RDL) structure, an electronic device, a first reinforcement structure, a second reinforcement structure, and an encapsulant. The RDL structure has a passivation layer and a patterned conductive layer disposed in the passivation layer. The electronic device is disposed on the RDL structure. The first reinforcement structure is disposed on the RDL structure and has a first modulus. The second reinforcement structure is disposed on the first reinforcement structure and has a second modulus substantially less than the first modulus. The encapsulant is disposed on the RDL structure and encapsulates the electronic device, the first reinforcement structure and the second reinforcement structure.
    Type: Application
    Filed: January 21, 2020
    Publication date: July 22, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Fan-Yu MIN, Chen-Hung LEE, Hsiu-Chi LIU, Liang-Chun CHEN
  • Publication number: 20210225783
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a dielectric layer. The semiconductor device package further includes an antenna structure disposed in the dielectric layer. The semiconductor device package further includes a semiconductor device disposed on the dielectric layer. The semiconductor device package further includes an encapsulant covering the semiconductor device. The semiconductor device package further includes a conductive pillar having a first portion and a second portion. The first portion surrounded by the encapsulant and the second portion embedded in the dielectric layer.
    Type: Application
    Filed: January 16, 2020
    Publication date: July 22, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ya Fang CHAN, Yuan-Feng CHIANG, Po-Wei LU
  • Publication number: 20210225746
    Abstract: A semiconductor package includes a base material, a capture land, an interconnection structure, a semiconductor chip and an encapsulant. The base material has a top surface and an inner lateral surface. The capture land is disposed in or on the base material, and has an outer side surface. The interconnection structure is disposed along the inner lateral surface of the base material, and on the capture land. The interconnection structure has an outer side surface. An outer side surface of the semiconductor package includes the outer side surface of the capture land and the outer side surface of the interconnection structure. The semiconductor chip is disposed on the top surface of the base material. The encapsulant is disposed adjacent to the top surface of the base material, and covers the semiconductor chip.
    Type: Application
    Filed: April 2, 2021
    Publication date: July 22, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Bernd Karl APPELT, You-Lung YEN, Kay Stefan ESSIG
  • Publication number: 20210217677
    Abstract: A semiconductor package includes a substrate, an electronic component and a first dilatant layer. The electronic component is disposed on the substrate. The electronic component has a top surface, a bottom surface opposite to the top surface and a lateral surface extending between the top surface and the bottom surface. The first dilatant layer is disposed on the top surface of the electronic component and extends along the lateral surface of the electronic component.
    Type: Application
    Filed: January 9, 2020
    Publication date: July 15, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen-Long LU
  • Publication number: 20210217701
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first semiconductor device, a first conductive layer and a second conductive layer. The first semiconductor device has a first conductive pad. The first conductive layer is disposed in direct contact with the first conductive pad. The first conductive layer extends along a direction substantially parallel to a surface of the first conductive pad. The second conductive layer is disposed in direct contact with the first conductive pad and spaced apart from the first conductive layer.
    Type: Application
    Filed: January 14, 2020
    Publication date: July 15, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Min Lung HUANG, Hung-Jung TU, Hsin Hsiang WANG, Chih-Wei HUANG, Shiuan-Yu LIN
  • Publication number: 20210206628
    Abstract: A semiconductor package structure includes a die paddle, a plurality of leads, an electronic component and a package body. Each of the plurality of leads is separated from the die paddle and has an inner side surface facing the die paddle. The electronic component is disposed on the die paddle. The package body covers the die paddle, the plurality of leads and the electronic component. The package body is in direct contact with a bottom surface of the die paddle and the inner side surface of the plurality of leads.
    Type: Application
    Filed: January 3, 2020
    Publication date: July 8, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Hsuan TSAI, Lu-Ming LAI, Chien-Wei FANG, Ching-Han HUANG
  • Publication number: 20210210662
    Abstract: A semiconductor device package includes a carrier, a die, an encapsulation layer and a thickness controlling component. The die is disposed on the carrier, wherein the die includes a first surface. The encapsulation layer is disposed on the carrier, and encapsulates a portion of the first surface of the die. The encapsulation layer defines a space exposing another portion of the first surface of the die. The thickness controlling component is disposed in the space.
    Type: Application
    Filed: January 3, 2020
    Publication date: July 8, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yi Wen CHIANG, Kuang-Hsiung CHEN, Lu-Ming LAI, Hsun-Wei CHAN, Hsin-Ying HO, Shih-Chieh TANG
  • Publication number: 20210210420
    Abstract: A semiconductor device package includes a first dielectric layer, a conductive pad and an electrical contact. The first dielectric layer has a first surface and a second surface opposite to the first surface. The conductive pad is disposed within the first dielectric layer. The conductive pad includes a first conductive layer and a barrier. The first conductive layer is adjacent to the second surface of the first dielectric layer. The first conductive layer has a first surface facing the first surface of the first dielectric layer and a second surface opposite to the first surface. The second surface of the first conductive layer is exposed from the first dielectric layer. The barrier layer is disposed on the first surface of the first conductive layer. The electrical contact is disposed on the second surface of the first conductive layer of the conductive pad.
    Type: Application
    Filed: March 16, 2021
    Publication date: July 8, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yung-Shun CHANG, Teck-Chong LEE
  • Publication number: 20210210446
    Abstract: A semiconductor device package includes a redistribution structure and an electrical connection. The redistribution structure has an electrical terminal adjacent to a surface of the redistribution structure and a seed layer covering a side surface of the electrical terminal. The electrical connection is disposed on a first surface of the electrical terminal. The seed layer extends to the first surface of the electrical terminal.
    Type: Application
    Filed: January 6, 2020
    Publication date: July 8, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Lin HO, Chih-Cheng LEE
  • Publication number: 20210210536
    Abstract: A semiconductor package includes a semiconductor device and a second substrate. The semiconductor device is disposed on, and electrically connected to, the second substrate. The semiconductor device includes a first substrate and a multi-layered structure. The multi-layered structure is disposed on a top surface of the first substrate and a layer of the multi-layered structure extends outwardly beyond a lateral edge of a topmost surface of the multi-layered structure.
    Type: Application
    Filed: January 3, 2020
    Publication date: July 8, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wei-Wei LIU, Huei-Siang WONG
  • Publication number: 20210210398
    Abstract: A semiconductor device package includes a substrate, a first electronic component and a first encapsulant. The substrate has a first surface and a second surface opposite to the first surface. The first electronic component is disposed on the first surface of the substrate. The first encapsulant is disposed on the first surface of the substrate and covers the first electronic component. The first encapsulant has a first surface facing away the first surface of the substrate and includes a recess at an edge of the first surface of the first encapsulant.
    Type: Application
    Filed: January 3, 2020
    Publication date: July 8, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen-Long LU
  • Publication number: 20210210433
    Abstract: A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a first carrier, an encapsulant, a second carrier and one or more supporters. The first carrier has a first surface and a first side contiguous with the first surface. The encapsulant is on the first surface of the first carrier, and the first side of the first carrier is exposed from the encapsulant. The second carrier is disposed over the first carrier. The one or more supporters are spaced apart from the first side of the first carrier and connected between the first carrier and the second carrier. The one or more supporters are arranged asymmetrically with respect to the geographic center of the first carrier. The one or more supporters are fully sealed in the encapsulant.
    Type: Application
    Filed: January 6, 2020
    Publication date: July 8, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Chao Wei LIU
  • Publication number: 20210210423
    Abstract: A semiconductor package structure includes a semiconductor die and at least one pillar structure. The semiconductor die has an upper surface and includes at least one conductive pad disposed adjacent to the upper surface. The pillar structure is electrically connected to the conductive pad of the semiconductor die, and defines a recess portion recessed from a side surface of the pillar structure. A conductivity of the pillar structure is greater than a conductivity of the conductive pad.
    Type: Application
    Filed: January 8, 2020
    Publication date: July 8, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yung-Shun CHANG, Meng-Wei HSIEH, Teck-Chong LEE
  • Publication number: 20210202349
    Abstract: A semiconductor device package includes a semiconductor die and an anisotropic thermal conductive structure. The semiconductor die includes a first surface, a second surface opposite to the first surface and edges connecting the first surface to the second surface. The anisotropic thermal conductive structure has different thermal conductivities in different directions. The anisotropic thermal conductive structure includes at least two pairs of film stacks, and each pair of the film stacks comprises a metal film and a nano-structural film alternately stacked. The anisotropic thermal conductive structure comprises a first thermal conductive section disposed on the first surface of the semiconductor die, and the first thermal conductive section is wider than the semiconductor die.
    Type: Application
    Filed: December 30, 2019
    Publication date: July 1, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsin-En CHEN, Hung-Hsien HUANG, Shin-Luh TARNG
  • Publication number: 20210202362
    Abstract: A semiconductor package includes a core layer, a conductive interconnect and a semiconductor chip. The core layer has a top surface and a bottom surface opposite to the top surface. The conductive interconnect penetrates through the core layer. The conductive interconnect has a top surface and a bottom surface respectively exposed from the top surface and the bottom surface of the core layer. The semiconductor chip is disposed on the top surface of the core layer. The semiconductor chip includes a conductive pad, and the top surface of the conductive interconnect directly contacts the conductive pad.
    Type: Application
    Filed: December 31, 2019
    Publication date: July 1, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: You-Lung YEN, Bernd Karl APPELT