Patents Assigned to Advanced Semiconductor Engineering
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Publication number: 20210343671Abstract: A semiconductor package structure includes a first semiconductor die having an active surface and a passive surface opposite to the active surface, a conductive element leveled with the first semiconductor die, a first redistribution layer (RDL) being closer to the passive surface than to the active surface, a second RDL being closer to the active surface than to the passive surface, and a second semiconductor die over the second RDL and electrically coupled to the first semiconductor die through the second RDL. A first conductive path is established among the first RDL, the conductive element, the second RDL, and the active surface of the first semiconductor die.Type: ApplicationFiled: July 13, 2021Publication date: November 4, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chi-Han CHEN, Hung-Yi LIN
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Publication number: 20210343664Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first electronic component having an active surface and a backside surface opposite to the active surface and a first antenna layer disposed on the backside surface of the first electronic component. The semiconductor device package further includes a first dielectric layer covering the first antenna layer and a second antenna layer disposed over the first antenna layer. The second antenna layer is spaced apart from the first antenna layer by the first dielectric layer. A method of manufacturing a semiconductor device package is also disclosed.Type: ApplicationFiled: April 29, 2020Publication date: November 4, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Wei-Tung CHANG, Cheng-Nan LIN
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Publication number: 20210343632Abstract: A package structure and a method for manufacturing a package structure are provided. The package structure includes a substrate, at least one redistribution structure, at least one electronic component and at least one semiconductor die. The substrate has a first surface and a second surface opposite to the first surface. The at least one redistribution structure is disposed on the first surface of the substrate. The at least one electronic component is disposed on the first surface of the substrate. The at least one semiconductor die is disposed on the at least one redistribution structure and electrically connected to the at least one electronic component through the substrate.Type: ApplicationFiled: April 29, 2020Publication date: November 4, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventor: Wen Hung HUANG
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Publication number: 20210335742Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate and a metal holder. The substrate includes at least one bonding pad disposed adjacent to its surface and the metal holder is disposed adjacent to the bonding pad.Type: ApplicationFiled: April 28, 2020Publication date: October 28, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: You-Lung YEN, Bernd Karl APPELT
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Publication number: 20210335729Abstract: A semiconductor package device includes a wiring structure, a semiconductor chip and an encapsulant. The semiconductor chip is electrically connected to the wiring structure. The encapsulant is disposed on the wiring structure and covers the semiconductor chip. A roughness (Ra) of a surface of the encapsulant is about 5 nm to about 50 nm.Type: ApplicationFiled: July 6, 2021Publication date: October 28, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventor: Wen-Long LU
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Publication number: 20210335715Abstract: A package structure and a method for manufacturing a package structure are provided. The package structure includes a first conductive structure and a second conductive structure. The first conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The second conductive structure is bonded to the first conductive structure. The second conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. A distribution density of the circuit layer of the first conductive structure is greater than a distribution density of the circuit layer of the second conductive structure. A size of the second conductive structure is less than a size of the first conductive structure.Type: ApplicationFiled: April 24, 2020Publication date: October 28, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventor: Chin-Li KAO
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Publication number: 20210327819Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.Type: ApplicationFiled: April 17, 2020Publication date: October 21, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG
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Publication number: 20210327815Abstract: A substrate, a semiconductor package device and a method of manufacturing a semiconductor device package are provided. The substrate includes a low density wiring structure, a first middle density wiring structure and high density wiring structure. The first middle density wiring structure is electrically connected to the low density wiring structure. The high density wiring structure is electrically connected to the low density wiring structure. The high density wiring structure and the first middle density wiring structure are disposed side by side. A line space of a circuit layer of the low density wiring structure is greater than a line space of a circuit layer of the first middle density wiring structure. The line space of the circuit layer of the first middle density wiring structure is greater than a line space of a circuit layer of the high density wiring structure.Type: ApplicationFiled: April 16, 2020Publication date: October 21, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Ian HU, Shin-Luh TARNG
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Publication number: 20210327822Abstract: A semiconductor device package includes a substrate having a surface, a conductive element disposed on the surface of the substrate, and an encapsulant disposed on the surface of the substrate and covering the conductive element. The conductive element has an upper surface facing away from the substrate and exposed from the encapsulant. Further, a roughness of the upper surface of the conductive element is greater than a roughness of a side surface of the conductive element.Type: ApplicationFiled: April 17, 2020Publication date: October 21, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Wei Da LIN, Meng-Jen WANG, Hung Chen KUO, Wen Jin HUANG
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Publication number: 20210327796Abstract: A wiring structure is provided. The wiring structure includes an upper redistribution structure, a lower redistribution structure, a conductive structure, an upper bonding layer and a lower bonding layer. The conductive structure is disposed between and electrically connected to the upper redistribution structure and the lower redistribution structure. The upper bonding layer is disposed between the upper redistribution structure and the conductive structure to bond the upper redistribution structure and the conductive structure together. The lower bonding layer is disposed between the lower redistribution structure and the conductive structure to bond the lower redistribution structure and the conductive structure together.Type: ApplicationFiled: April 20, 2020Publication date: October 21, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Tang-Yuan CHEN, Chih-Pin HUNG
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Publication number: 20210327731Abstract: A mass transfer method, a mass transfer device and a buffer carrier are provided. The mass transfer method includes: (a) providing a plurality of electronic components disposed on a source carrier; (b) providing a buffer carrier including a plurality of adjusting cavities; and (c) transferring the electronic components from the source carrier to the buffer carrier, wherein the electronic components are placed in the adjusting cavities of the buffer carrier to adjust positions of the electronic components from shifted positions to correct positions.Type: ApplicationFiled: April 15, 2020Publication date: October 21, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chih-Wen CHANG, Yu-Ho HSU, Tai-Yuan HUANG, Ping-Feng YANG, Fu-Ting CHANG, Chin-Feng WANG
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Publication number: 20210327841Abstract: A package structure and a manufacturing method are provided. The package structure includes a first circuit layer, a first dielectric layer, an electrical device and a first conductive structure. The first circuit layer includes a first alignment portion. The first dielectric layer covers the first circuit layer. The electrical device is disposed on the first dielectric layer, and includes an electrical contact aligning with the first alignment portion. The first conductive structure extends through the first alignment portion, and electrically connects the electrical contact and the first alignment portion.Type: ApplicationFiled: April 21, 2020Publication date: October 21, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: You-Lung YEN, Bernd Karl APPELT
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Publication number: 20210320038Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a substrate having a central region and a periphery surrounding the central region, and an electronic component disposed on the substrate. The substrate includes a plurality of testing contacts disposed within the periphery and spaced apart from each other. The electronic component includes a dummy pad. The dummy pad covers two of the plurality of the testing contacts and laterally spaced apart from the other of the plurality of the testing contacts. A method of semiconductor device package alignment inspection is also provided.Type: ApplicationFiled: April 9, 2020Publication date: October 14, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Ting Wei HSU, Pei-Jen LO, Shun-Tsat TU
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Publication number: 20210313476Abstract: An optical sensor package structure and an optical module structure are provided. The optical sensor package structure includes a substrate, a sensor device and a transparent encapsulant. The sensor device is electrically connected to the substrate, and has a sensing area facing the substrate. The transparent encapsulant covers the sensing area of the sensor device.Type: ApplicationFiled: April 2, 2020Publication date: October 7, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chun Yu KO, Tsu-Hsiu WU, Wei-Tang CHU
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Publication number: 20210305441Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a substrate including a sensing region and a first transparent layer disposed over the sensing region. The first transparent layer has a first surface facing the sensing region, a second surface opposite to the first surface of the first transparent layer, and a lateral surface extending between the first surface and the second surface of the first transparent layer. The semiconductor device package further includes a first light blocking layer disposed on the first transparent layer. The first light blocking layer defines a plurality of apertures. At least a portion of the first light blocking layer extends over the lateral surface of the first transparent layer. A semiconductor package assembly is also disclosed.Type: ApplicationFiled: March 31, 2020Publication date: September 30, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Wei-Wei LIU, Huei-Siang WONG
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Publication number: 20210305180Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes an antenna layer, a first circuit layer and a second circuit layer. The antenna layer has a first coefficient of thermal expansion (CTE). The first circuit layer is disposed over the antenna layer. The first circuit layer has a second CTE. The second circuit layer is disposed over the antenna layer. The second circuit layer has a third CTE. A difference between the first CTE and the second CTE is less than a difference between the first CTE and the third CTE.Type: ApplicationFiled: March 27, 2020Publication date: September 30, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventor: Wen Hung HUANG
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Publication number: 20210305192Abstract: A semiconductor device package includes a first electronic device and a second electronic device. The first electronic device includes a first redistribution layer (RDL) including a circuit layer. The second electronic device is disposed on the first RDL of the first electronic device. The second electronic device includes an encapsulant and a patterned conductive layer. The encapsulant has a first surface facing the first RDL of the first electronic device, and a second surface opposite to the first surface. The patterned conductive layer is disposed at the second surface of the encapsulant, and is configured to be electrically coupled to the circuit layer of the first RDL of the first electronic device.Type: ApplicationFiled: June 14, 2021Publication date: September 30, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Ming Hsien CHU, Chi-Yu WANG
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Publication number: 20210305181Abstract: An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.Type: ApplicationFiled: June 14, 2021Publication date: September 30, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Cheng-Nan LIN, Wei-Tung CHANG, Jen-Chieh KAO, Huei-Shyong CHO
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Publication number: 20210296230Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes an upper conductive structure, a lower conductive structure and a redistribution structure. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The redistribution structure is disposed between the upper conductive structure and the lower conductive structure to electrically connect the upper conductive structure and the lower conductive structure. The redistribution structure includes a dielectric structure and a redistribution layer embedded in the dielectric structure. The redistribution layer includes at least one circuit layer.Type: ApplicationFiled: March 17, 2020Publication date: September 23, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventor: Wen Hung HUANG
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Publication number: 20210298176Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.Type: ApplicationFiled: June 8, 2021Publication date: September 23, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Fan CHEN, Chien-Hao WANG
