Patents Assigned to Advanced Semiconductor Engineering
  • Publication number: 20220068831
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first device, a second device, and a shielding structure. The first device and the second device is one a first side of a substrate. The shielding structure includes a first portion and a second portion. The first portion is between the first device and the second device on the substrate, and the first portion includes a plurality of first shielding units arranged along a first direction. The second portion is between the first device and the second device, and the second portion includes a plurality of second shielding units arranged along a second direction different from the first direction. The second portion is configured as a first waveguide between the first device and the second device.
    Type: Application
    Filed: September 1, 2020
    Publication date: March 3, 2022
    Applicant: Advanced Semiconductor Engineering Korea, Inc.
    Inventors: Soonheung BAE, Jyhwan LEE, Jaeshin CHO
  • Publication number: 20220068774
    Abstract: A semiconductor device package includes a substrate and a conductive lid. The conductive lid is disposed within the substrate. The conductive lid defines a waveguide having a cavity. The waveguide is configured to transmit a signal from a first electronic component to a second electronic component through the cavity.
    Type: Application
    Filed: September 2, 2020
    Publication date: March 3, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Shih-Wen LU
  • Publication number: 20220068839
    Abstract: A package structure and a manufacturing method are provided. The package structure includes a wiring structure, a first electronic device, a second electronic device, a first underfill, a second underfill and a stiff bonding material. The first electronic device and the second electronic device are disposed on the wiring structure, and are electrically connected to each other through the wiring structure. The first underfill is disposed in a first space between the first electronic device and the wiring structure. The second underfill is disposed in a second space between the second electronic device and the wiring structure. The stiff bonding material is disposed in a central gap between the first electronic device and the second electronic device. The stiff bonding material is different from the first underfill and the second underfill.
    Type: Application
    Filed: August 26, 2020
    Publication date: March 3, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Po-Hsien KE, Teck-Chong LEE, Chih-Pin HUNG
  • Publication number: 20220059406
    Abstract: The present disclosure provides a method for manufacturing a semiconductor package. The method includes disposing a first semiconductor substrate on a temporary carrier and dicing the first semiconductor substrate to form a plurality of dies. Each of the plurality of dies has an active surface and a backside surface opposite to the active surface. The backside surface is in contact with the temporary carrier and the active surface faces downward. The method also includes transferring one of the plurality of dies from the temporary carrier to a temporary holder. The temporary holder only contacts a periphery portion of the active surface of the one of the plurality of dies.
    Type: Application
    Filed: August 21, 2020
    Publication date: February 24, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Hsu-Nan FANG
  • Publication number: 20220056589
    Abstract: An electroless semiconductor bonding structure, an electroless plating system and an electroless plating method of the same are provided. The electroless semiconductor bonding structure includes a first substrate and a second substrate. The first substrate includes a first metal bonding structure disposed adjacent to a first surface of the first substrate. The second substrate includes a second metal bonding structure disposed adjacent to a second surface of the second substrate. The first metal bonding structure connects to the second metal bonding structure at an interface by electroless bonding and the interface is substantially void free.
    Type: Application
    Filed: August 21, 2020
    Publication date: February 24, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chun-Wei CHIANG, Shin-Luh TARNG, Chih-Pin HUNG, Shiu-Chih WANG, Yong-Da CHIU
  • Publication number: 20220052004
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a conductive pillar having a first surface, a second surface, and a lateral surface extending between the first surface and the second surface. The lateral surface has a first part and a second part connected to the first part. The semiconductor device package also includes a barrier layer in contact with the first part of the lateral surface of the conductive pillar and an encapsulant in contact with the second part of the lateral surface of the conductive pillar. The semiconductor device package also includes a first flowable conductive material disposed on the first surface of the conductive pillar. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Application
    Filed: August 14, 2020
    Publication date: February 17, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Zhi-Yuan LIN
  • Publication number: 20220052024
    Abstract: A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a first module, a second module, a first intermediate circuit layer, a first conductive transmission path and a second conductive transmission path. The second module is stacked on the first module. The first intermediate circuit layer is arranged between the first module and the second module. The first conductive transmission is configured to electrically connect the first semiconductor module with the first intermediate circuit layer. The second conductive transmission path is configured to electrically connect the first intermediate circuit layer with the second semiconductor module.
    Type: Application
    Filed: August 14, 2020
    Publication date: February 17, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen-Long LU
  • Publication number: 20220052013
    Abstract: A semiconductor device package is provided. The semiconductor device package includes providing a first substrate, a computing unit and a power module. The first substrate has a first surface and a second surface opposite to the first surface. The computing unit is adjacent to the first surface. The computing unit includes a semiconductor die. The power module is adjacent to the second surface. The power module includes a power element and a passive element. Each of the semiconductor die, the power element, and the passive element is vertically arranged with respect to each other, and the passive elements are assembled between the semiconductor die and the power element.
    Type: Application
    Filed: October 26, 2021
    Publication date: February 17, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Han-Chee YEN, Ying-Nan LIU, Min-Yao CHENG
  • Publication number: 20220043215
    Abstract: A recessed portion in a semiconductor substrate and a method of forming the same are provided. The method comprises: forming a mask on the semiconductor substrate; forming a protection layer on a top surface of the mask and on at least one sidewall of the mask, and on at least one surface of the semiconductor substrate exposed by the mask; performing a first etching process to remove the protection layer on the top surface of the mask and on a bottom surface of the semiconductor substrate exposed by the mask; and performing a second etching process to remove the remaining protection layer and to etch the semiconductor substrate to form the recessed portion. In this way, a recessed portion with relatively smooth and vertical sidewalls can be realized.
    Type: Application
    Filed: August 7, 2020
    Publication date: February 10, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shao Hsuan CHUANG, Huang-Hsien CHANG
  • Publication number: 20220037244
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first substrate and a second substrate. The first substrate has a first surface and a second surface opposite to the first surface of the first substrate. The second substrate has a first surface facing the first substrate and a second surface opposite to the first surface of the second substrate. The semiconductor device package also includes a first electronic component disposed on the first surface of the second substrate and electrically connected to the first surface of the second substrate. The semiconductor device package also includes a first encapsulant and a second encapsulant between the first substrate and the second substrate. The first encapsulant is different from the second encapsulant. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Application
    Filed: August 3, 2020
    Publication date: February 3, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Li-Hua TAI, Wen-Pin HUANG
  • Publication number: 20220037290
    Abstract: A semiconductor device package includes a substrate, a stacked structure and an encapsulation layer. The substrate includes a circuit layer, a first surface and a second surface opposite to the first surface. The substrate defines at least one cavity through the substrate. The stacked structure includes a first semiconductor die disposed on the first surface and electrically connected on the circuit layer, and at least one second semiconductor die stacked on the first semiconductor die and electrically connected to the first semiconductor die. The second semiconductor die is at least partially inserted into the cavity. The encapsulation layer is disposed in the cavity and at least entirely encapsulating the second semiconductor die.
    Type: Application
    Filed: October 12, 2021
    Publication date: February 3, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: You-Lung YEN, Bernd Karl APPELT, Kay Stefan ESSIG
  • Publication number: 20220037242
    Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes a conductive structure and at least one conductive through via. The conductive structure includes a plurality of dielectric layers, a plurality of circuit layers in contact with the dielectric layers, and a plurality of dam portions in contact with the dielectric layers. The dam portions are substantially arranged in a row and spaced apart from one another. The conductive through via extends through the dam portions.
    Type: Application
    Filed: July 31, 2020
    Publication date: February 3, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Min Lung HUANG
  • Publication number: 20220028596
    Abstract: An inductor unit includes a conductive structure, a first magnetic element and an insulating layer. The conductive structure has a bottom conductive layer, a top conductive layer, and a first side conductive layer extending from the bottom conductive layer to the top conductive layer. The first magnetic element is disposed on the bottom conductive layer of the conductive structure. The insulating layer is disposed on the bottom conductive layer of the conductive structure, wherein the insulating layer covers and surrounds the first magnetic element. The circuit structure including the inductor unit and the methods for manufacturing the same are also provided.
    Type: Application
    Filed: July 23, 2020
    Publication date: January 27, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Syu-Tang LIU, Huang-Hsien CHANG, Yunghsun CHEN
  • Publication number: 20220028800
    Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a die and a stiffener. The substrate has an upper surface. The die is disposed on the upper surface of the substrate. The stiffener is disposed on the upper surface of the substrate and surrounds the die. The stiffener has a first upper surface adjacent to the die, a second upper surface far from the die and a lateral surface extending from the first upper surface to the second upper surface. A first distance between the first upper surface of the stiffener and the upper surface of the substrate is less than a second distance between the second upper surface of the stiffener and the upper surface of the substrate.
    Type: Application
    Filed: July 24, 2020
    Publication date: January 27, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jui-Tzu CHEN, Yu-Hsing LIN, Chia-Chieh HU, Chun-Cheng KUO, Yu-Hsiang CHAO
  • Publication number: 20220028836
    Abstract: A semiconductor device package includes a substrate, a connection structure, a first package body and a first electronic component. The substrate has a first surface and a second surface opposite to the first surface. The connection structure is disposed on the first surface of the substrate. The first package body is disposed on the first surface of the substrate. The first package body covers the connection structure and exposes a portion of the connection structure. The first electronic component is disposed on the first package body and in contact with the portion of the connection structure exposed from the first package body.
    Type: Application
    Filed: October 4, 2021
    Publication date: January 27, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shang-Ruei WU, Chien-Yuan TSENG, Meng-Jen WANG, Chen-Tsung CHANG, Chih-Fang WANG, Cheng-Han LI, Chien-Hao CHEN, An-Chi TSAO, Per-Ju CHAO
  • Publication number: 20220028801
    Abstract: A semiconductor device package and method for manufacturing the same are provided. The semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, and a first circuit layer disposed on the substrate. The first circuit layer includes a conductive wiring pattern, and the conductive wiring pattern is an uppermost conductive pattern of the first circuit layer. The stress buffering structure is disposed on the first conductive structure. The second conductive structure is disposed over the stress buffering structure. The conductive wiring pattern extends through the stress buffering structure and electrically connected to the second conductive structure, and an upper surface of the conductive wiring pattern is substantially coplanar with an upper surface of the stress buffering structure.
    Type: Application
    Filed: July 24, 2020
    Publication date: January 27, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsing Kuo TIEN, Chih-Cheng LEE
  • Publication number: 20220028817
    Abstract: At least some embodiments of the present disclosure relate to a method for manufacturing a bonding structure. The method includes: providing a substrate with a seed layer; forming a conductive pattern on the seed layer; forming a dielectric layer on the substrate and the conductive pattern; and removing a portion of the dielectric layer to expose an upper surface of the conductive pattern without consuming the seed layer.
    Type: Application
    Filed: July 23, 2020
    Publication date: January 27, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shao Hsuan CHUANG, Huang-Hsien CHANG
  • Publication number: 20220020885
    Abstract: An optical device includes a first circuit layer, a light detector, a first conductive pillar and an encapsulant. The first circuit layer has an interconnection layer and a dielectric layer. The light detector is disposed on the first circuit layer. The light detector has a light detecting area facing away from the first circuit layer and a backside surface facing the first circuit layer. The first conductive pillar is disposed on the first circuit layer and spaced apart from the light detector. The first conductive pillar is electrically connected to the interconnection layer of the first circuit layer. The encapsulant is disposed on the first circuit layer and covers the light detector and the first conductive pillar. The light detector is electrically connected to the interconnection layer of the first circuit layer through the first conductive pillar. The backside surface of the light detector is exposed from the encapsulant.
    Type: Application
    Filed: September 28, 2021
    Publication date: January 20, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Pin TSAI, Tsung-Yueh TSAI, Teck-Chong LEE
  • Publication number: 20220020605
    Abstract: A semiconductor package structure and a method of manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a conductive base, a first semiconductor die, a first conductive pillar, and a first encapsulant. The conductive base has a first surface. The first semiconductor die is disposed on the first surface of the conductive base. The first conductive pillar is disposed on the first semiconductor die. The first encapsulant is disposed on the first surface of the conductive base. The first encapsulant encapsulates the first semiconductor die. The first encapsulant includes an opening defined by the first conductive pillar.
    Type: Application
    Filed: July 20, 2020
    Publication date: January 20, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Kay Stefan ESSIG, Jean Marc YANNOU, Bradford FACTOR
  • Publication number: 20220020698
    Abstract: The present disclosure provides an electronic package and method of manufacturing the same. The electronic package includes an electronic device including a first carrier and a first electronic component disposed on the first carrier, a second carrier adjacent to the first carrier of the electronic device, and a conductive layer at least partially covering the electronic device, and separating the electronic device from the second carrier.
    Type: Application
    Filed: July 16, 2020
    Publication date: January 20, 2022
    Applicant: Advanced Semiconductor Engineering Korea, Inc.
    Inventors: Seokbong KIM, Eunshim LEE