Patents Assigned to Advanced Semiconductor Engineering
  • Wearable component, ear tip, and method of manufacturing a wearable component
    Patent number: 12185047
    Abstract: The present disclosure provides a wearable component. The wearable component includes a first carrier and a first electronic component at least partially embedded within the first carrier. The first carrier and the first electronic component define a space configured for audio transmission. An ear tip and a method of manufacturing a wearable component are also provided.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: December 31, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang Yi Wu, Hung Yi Lin, Jenchun Chen
  • Electronic package structure
    Patent number: 12183683
    Abstract: An electronic package structure includes an electronic structure, a wiring structure, an electrical contact and a support layer. The wiring structure is located over the electronic structure. The electrical contact connects the wiring structure and the electronic structure. The support layer is disposed around the electrical contact and has a surface facing the electrical contact. The surface includes at least one inflection point in a cross-sectional view.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: December 31, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wei-Jen Wang, Po-Jen Cheng, Fu-Yuan Chen
  • Method and system for manufacturing a semiconductor package structure
    Patent number: 12183712
    Abstract: A method and a system for manufacturing a semiconductor package structure are provided. The method includes: (a) providing a package body including at least one semiconductor device encapsulated in an encapsulant; (b) providing a flattening force to the package body; (c) thinning the package body after (b); (d) attaching a film to the package body; and (e) releasing the flattening force after (d).
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: December 31, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Che-Ting Liu, Jheng-Yu Hong, Yu-Ting Lu, Po-Chun Lee, Chih-Hsiang Hsu
  • Electronic package structure
    Patent number: 12184266
    Abstract: The present disclosure provides a semiconductor package structure. The semiconductor package structure includes a substrate, a first electronic component and a support component. The first electronic component is disposed on the substrate. The first electronic component has a backside surface facing a first surface of the substrate. The support component is disposed between the backside surface of the first electronic component and the first surface of the substrate. The backside surface of the first electronic component has a first portion connected to the support component and a second portion exposed from the support component.
    Type: Grant
    Filed: February 21, 2023
    Date of Patent: December 31, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chi Sheng Tseng, Lu-Ming Lai, Ching-Han Huang, Kuo-Hua Lai, Hui-Chung Liu
  • Manufacturing method for manufacturing a package structure
    Patent number: 12183593
    Abstract: A manufacturing method for manufacturing a package structure is provided. The manufacturing method includes: (a) providing a carrier having a top surface and a lateral side surface, wherein the top surface includes a main portion and a flat portion connecting the lateral side surface, and a first included angle between the main portion and the flat portion is less than a second included angle between the main portion and the lateral side surface; (b) forming an under layer on the carrier to at least partially expose the flat portion; and (c) forming a dielectric layer on the under layer and covering the exposed flat portion.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: December 31, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chia-Pin Chen, Chia Sheng Tien, Wan-Ting Chiu, Chi Long Tsai, Cyuan-Hong Shih, Yen Liang Chen
  • SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20240429115
    Abstract: A semiconductor package device includes a first substrate, a second substrate and a first spacer. The first substrate includes a first divided pad. The second substrate includes a second divided pad disposed above the first divided pad. The first spacer is disposed between the first divided pad and the second divided pad. The first spacer is in contact with the first divided pad and the second divided pad.
    Type: Application
    Filed: September 10, 2024
    Publication date: December 26, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yi CHEN, Chang-Lin YEH, Jen-Chieh KAO
  • OPTICAL MODULE
    Publication number: 20240427092
    Abstract: The present disclosure provides an optical module. The optical module includes an optical component disposed in or on a carrier and configured to receive a first light. The optical component is further configured to transmit a second light to a first portion of the carrier and transmit a third light to a second portion of the carrier.
    Type: Application
    Filed: September 10, 2024
    Publication date: December 26, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shih-Chieh TANG, Lu-Ming LAI, Yu-Che HUANG, Ying-Chung CHEN
  • ELECTRONIC DEVICE
    Publication number: 20240429213
    Abstract: An electronic device is provided. The electronic device includes a package structure and a power regulating element. The package structure includes an electronic component, a plurality of first conductive structures, and an encapsulant. The plurality of first conductive structures are connected to the electronic component. The encapsulant encapsulates the electronic component and exposes a portion of the plurality of first conductive structures. The power regulating component includes a plurality of second conductive structures directly bonded with the plurality of first conductive structures and configured to provide the electronic component with a power signal.
    Type: Application
    Filed: June 20, 2023
    Publication date: December 26, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Syu-Tang LIU, Pao-Nan LEE, Yu-Hsun CHANG, Jung Jui KANG
  • Semiconductor device package
    Patent number: 12176297
    Abstract: A semiconductor device package includes a first substrate, a second substrate, a first electronic component, a second electronic component and a shielding layer. The second substrate is disposed over the first substrate. The first electronic component is disposed between the first substrate and the second substrate. The second electronic component is disposed between the first substrate and the second substrate and adjacent to the second substrate than the first electronic component. The shielding element electrically connects the second electronic component to the second substrate. The second electronic component and the shielding element define a space accommodating the first electronic component.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: December 24, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hao-Chih Hsieh, Tzu-Cheng Lin, Chun-Jen Chen
  • Semiconductor device package and method for manufacturing the same
    Patent number: 12176276
    Abstract: A semiconductor device package includes a first substrate, a second substrate, a conductive structure, a first solder and a second solder. The second substrate is disposed over the first substrate. The conductive structure is disposed between the first substrate and the second substrate. The conductive structure includes a first wetting portion, a second wetting portion, and a non-wetting portion disposed between the first wetting portion and the second wetting portion. The first solder covers the first wetting portion and connects the conductive structure to the first substrate. The second solder covers the second wetting portion and connects the conductive structure to the second substrate. The first solder is spaced apart from the second solder by the non-wetting portion.
    Type: Grant
    Filed: April 11, 2023
    Date of Patent: December 24, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Chang-Lin Yeh
  • Semiconductor package structure
    Patent number: 12176259
    Abstract: A semiconductor package structure includes a circuit pattern structure, an encapsulant and an anchoring structure. The encapsulant is disposed on the circuit pattern structure. The anchoring structure is disposed adjacent to an interface between the encapsulant and the circuit pattern structure, and is configured to reduce a difference between a variation of expansion of the encapsulant and a variation of expansion of the circuit pattern structure in an environment of temperature variation.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: December 24, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yung-Shun Chang, Teck-Chong Lee
  • Method for manufacturing semiconductor package structure and clamp apparatus
    Patent number: 12176240
    Abstract: A method for manufacturing a semiconductor package structure and a clamp apparatus are provided. The method includes: (a) providing a package body disposed on a chuck, wherein the package body includes at least one semiconductor element encapsulated in an encapsulant; (b) moving a pressing tool transversely to above the package body; and (c) pressing the package body on the chuck through the pressing tool.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: December 24, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Yun Di Hong
  • Semiconductor device package and method of manufacturing the same
    Patent number: 12176295
    Abstract: A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a first carrier, an encapsulant, a second carrier and one or more supporters. The first carrier has a first surface and a first side contiguous with the first surface. The encapsulant is on the first surface of the first carrier, and the first side of the first carrier is exposed from the encapsulant. The second carrier is disposed over the first carrier. The one or more supporters are spaced apart from the first side of the first carrier and connected between the first carrier and the second carrier. The one or more supporters are arranged asymmetrically with respect to the geographic center of the first carrier. The one or more supporters are fully sealed in the encapsulant.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: December 24, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Chao Wei Liu
  • Semiconductor package with integrated voltage regulator device and separate bridge die
    Patent number: 12176305
    Abstract: An electronic device is disclosed. The electronic device includes a first electronic component and a power regulating structure configured to provide a first power to the first electronic component. The power regulating structure includes a first component and a second component at least partially overlapped with the first component from a top view.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: December 24, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Pao-Nan Lee, Chen-Chao Wang, Chang Chi Lee
  • SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20240421103
    Abstract: A semiconductor device package and a method for manufacturing a semiconductor device package are provided. The semiconductor device package includes a substrate, a clip, and a support structure. The clip is disposed on the substrate. The clip includes a first portion and a second portion separated from each other by a slit. The support structure is above the substrate and supports the clip. The support structure has a first surface and a second surface facing the first surface, and the first surface and the second surface define a gap.
    Type: Application
    Filed: August 27, 2024
    Publication date: December 19, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chia Hsiu HUANG, Chun Chen CHEN, Wei Chih CHO, Shao-Lun YANG
  • ELECTRONIC DEVICE
    Publication number: 20240421086
    Abstract: An electronic device is disclosed. The electronic device includes a first electronic component, a second electronic component, and a circuit structure. The circuit structure is supported by the first electronic component and the second electronic component. The circuit structure electrically connects the first electronic component to the second electronic component and is configured to provide the first electronic component and the second electronic component with a power.
    Type: Application
    Filed: June 16, 2023
    Publication date: December 19, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Pao-Nan LEE, Syu-Tang LIU, Yu-Hsun CHANG
  • Antenna device and method for manufacturing the same
    Patent number: 12170400
    Abstract: An antenna device and a method for manufacturing the same are provided. The antenna device includes a carrier, an antenna portion, a first portion and a second portion. The antenna portion is located on the carrier. The first portion is located on the carrier. The second portion is located on the carrier and is configured for blocking a material from entering the antenna area, wherein the material covers a lateral surface of the carrier.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: December 17, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jenchun Chen, Shyue-Long Louh
  • Semiconductor device package and a method of manufacturing the same
    Patent number: 12168605
    Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a substrate with a first groove and a semiconductor device. The first groove has a first portion, a second portion, and a third portion, and the second portion is between the first portion and the third portion. The semiconductor device includes a membrane and is disposed on the second portion of the first groove. The semiconductor device has a first surface adjacent to the substrate and opposite to the membrane. The membrane is exposed by the first surface.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: December 17, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Liang Hsiao, Lu-Ming Lai, Ching-Han Huang, Chia-Hung Shen
  • Sensing package, optical module and method for detecting light
    Patent number: 12169170
    Abstract: The present disclosure provides a sensing package. The sensing package includes a carrier configured to face an object to be inspected and an emitter disposed adjacent to the carrier. The emitter is configured to emit a first light propagating in a first direction. The sensing package further includes a component configured to change the first light into a second light propagating in a second direction different from the first direction. An optical module and a method for detecting light are also provided.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: December 17, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wei-Hao Chang
  • PACKAGE STRUCTURE
    Publication number: 20240413115
    Abstract: A package structure is provided. The package structure includes an electronic component, an encapsulant, a first conductive pillar, a first dielectric layer. The electronic component has an active surface. The encapsulant encapsulates the electronic component and exposes the active surface of the electronic component. The first conductive pillar is over the active surface of the electronic component, wherein an upper surface of the first conductive pillar includes a concave portion. The first dielectric layer is over the encapsulant and the active surface of the electronic component, wherein the first dielectric layer defines an opening exposing the concave portion of the first conductive pillar.
    Type: Application
    Filed: June 7, 2023
    Publication date: December 12, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Ling YEH, Yuan-Feng CHIANG, Chung-Hung LAI, Chin-Li KAO