Patents Assigned to Advanced Semiconductor Engineering
  • PACKAGE STRUCTURE
    Publication number: 20240413062
    Abstract: A package structure is provided. The package structure includes a wiring structure, a first element, and a plurality of first wires. The wiring structure has a first recess recessed from a first surface of the wiring structure. The first element is disposed over the first surface of the wiring structure. The first wires are disposed in the first recess and extending in a direction from the wiring structure to the first element. The first wires are configured to reduce an inclination of the first element with respect to the first surface of the wiring structure.
    Type: Application
    Filed: June 7, 2023
    Publication date: December 12, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Jen-Hao PAN
  • PACKAGE STRUCTURE
    Publication number: 20240413061
    Abstract: A package structure is provided. The package structure includes a substrate, a wiring structure, and a wire bundle structure. The wiring structure is over the substrate. The wire bundle structure is between the wiring structure and the substrate. The wire bundle structure includes a first wire bundle extending from the substrate and a second wire bundle extending from the wiring structure and contacting the first nanowire bundle. The wire bundle structure is configured to reduce a variation in a distance of a gap between the substrate and the wiring structure.
    Type: Application
    Filed: June 7, 2023
    Publication date: December 12, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: An-Hsuan HSU, Cheng-Yuan KUNG, Yaohsin CHOU
  • OPTOELECTRONIC PACKAGE STRUCTURE
    Publication number: 20240411096
    Abstract: An optoelectronic package structure is provided. The optoelectronic package structure includes a first photonic component and an optical interposer. The optical interposer includes a plurality of optical paths and optically coupled to the first photonic component. The optical interposer is configured to switch between the optical paths for transmitting an optical signal from the first photonic component.
    Type: Application
    Filed: June 9, 2023
    Publication date: December 12, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jr-Wei LIN, Mei-Ju LU, Sin-Yuan MU
  • Semiconductor device packages and methods of manufacturing the same
    Patent number: 12166009
    Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.
    Type: Grant
    Filed: August 29, 2023
    Date of Patent: December 10, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tang-Yuan Chen, Meng-Kai Shih, Teck-Chong Lee, Shin-Luh Tarng, Chih-Pin Hung
  • Semiconductor package structure and method for manufacturing the same
    Patent number: 12165982
    Abstract: A semiconductor package structure includes at least one first semiconductor die, at least one second semiconductor die and an encapsulant. The first semiconductor die has a first surface and includes a plurality of first pillar structures disposed adjacent to the first surface. The second semiconductor die is electrically connected to the first semiconductor die. The encapsulant covers the first semiconductor die and the second semiconductor die. A lower surface of the encapsulant is substantially coplanar with an end surface of each of the first pillar structures and a surface of the second semiconductor die.
    Type: Grant
    Filed: August 2, 2022
    Date of Patent: December 10, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chun-Jun Zhuang
  • Substrate, semiconductor device package and method of manufacturing the same
    Patent number: 12165963
    Abstract: A substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface disposed adjacent to the first surface of the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. A width of the first end of the first conductive via is smaller than a width of the second end of the first conductive via, and a width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via.
    Type: Grant
    Filed: September 29, 2023
    Date of Patent: December 10, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Lin Ho, Chih-Cheng Lee
  • Semiconductor device package
    Patent number: 12165984
    Abstract: A semiconductor device package includes a number of interposers mounted to the carrier, wherein the number of interposers may be arranged in an irregular pattern.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: December 10, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hao-Chih Hsieh, Tun-Ching Pi, Sung-Hung Chiang, Yu-Chang Chen
  • ELECTRONIC DEVICE AND INTERCONNECTION STRUCTURE
    Publication number: 20240395784
    Abstract: The present disclosure provides an electronic device. The electronic device includes a flexible carrier, an electronic component disposed over the flexible carrier, and a first flexible connection element configured to connect the flexible carrier and the electronic component. The first flexible connection element is configured to extend along a deformation direction of the electronic device. An interconnection structure is also provided.
    Type: Application
    Filed: May 25, 2023
    Publication date: November 28, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuei-Hao TSENG, Kai Hung WANG, Chih Lung LIN
  • Electronic device
    Patent number: 12156336
    Abstract: An electronic device is disclosed. The electronic device includes a carrier including a first portion, a second portion over the first portion, and a third portion connecting the first portion and the second portion. The electronic device also includes a first electronic component disposed between the first portion and the second portion. An active surface of the first electronic component faces the second portion. The electronic device also includes a second electronic component disposed over the second portion. The first portion is configured to transmit a first power signal to a backside surface of the first electronic component opposite to the active surface.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: November 26, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chiung-Ying Kuo, Hung-Chun Kuo, Pao-Nan Lee, Jung Jui Kang, Chang Chi Lee
  • Electronic package
    Patent number: 12155111
    Abstract: An electronic package and a method of manufacturing an electronic package are provided. The electronic package includes a carrier, an antenna substrate, and an electronic component. The carrier has a first surface and a second surface. The antenna substrate includes a resonant cavity and is disposed over the first surface. The antenna substrate is closer to the first surface than the second surface of the carrier. The electronic component is disposed between the antenna substrate and the second surface of the carrier.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: November 26, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chung Ju Yu, Shao-Lun Yang, Chun-Hung Yeh, Hong Jie Chen, Tsung-Wei Lu, Wei Shuen Kao
  • Semiconductor device package comprising antenna and communication module
    Patent number: 12154870
    Abstract: A semiconductor device package includes a first circuit layer, a first emitting device and a second emitting device. The first circuit layer has a first surface and a second surface opposite to the first surface. The first emitting device is disposed on the second surface of the first circuit layer. The first emitting device has a first surface facing the first circuit layer and a second surface opposite to the first surface. The first emitting device has a first conductive pattern disposed on the first surface of the first emitting device. The second emitting device is disposed on the second surface of the first emitting device. The second emitting device has a first surface facing the second surface of the first emitting device and a second surface opposite to the first surface. The second emitting device has a second conductive pattern disposed on the second surface of the emitting device.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: November 26, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Meng-Wei Hsieh, Kuo-Chang Kang
  • Semiconductor device package and method of manufacturing the same
    Patent number: 12148980
    Abstract: The present disclosure provides a semiconductor device package including a substrate, a waveguide component, and an antenna pattern. The substrate includes a feeding element. The waveguide component is disposed over the substrate. The antenna pattern is disposed over the substrate. The waveguide component is substantially aligned with the feeding element and the antenna pattern.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: November 19, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Christophe Zinck
  • Semiconductor device including an exposed solderable element
    Patent number: 12148679
    Abstract: A semiconductor device, a semiconductor package, and a method of manufacturing the same are provided. The semiconductor device includes an electronic component, a first thermal conductive layer, a second thermal conductive layer, and a solderable element. The first thermal conductive layer is disposed adjacent to a surface of the electronic component. The second thermal conductive layer is disposed on the first thermal conductive layer and exposes a portion of the first thermal conductive layer. The solderable element is disposed on the second thermal conductive layer.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: November 19, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Tun-Ching Pi
  • ELECTRONIC DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20240379567
    Abstract: An electronic device package includes a substrate, a first semiconductor die, a second semiconductor die and an encapsulant. The substrate includes a first surface, and a second surface opposite to the first surface. The substrate defines a cavity recessed from the first surface. The first semiconductor die is disposed in the cavity. The second semiconductor die is disposed over and electrically connected to the first semiconductor die. The encapsulant is disposed in the cavity of the substrate. The encapsulant encapsulates a first sidewall of the first semiconductor die, and exposes a second sidewall of the first semiconductor die.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Mei-Ju LU, Jr-Wei LIN
  • Semiconductor device package and method of manufacturing the same
    Patent number: 12142571
    Abstract: A semiconductor device package and a method for manufacturing the semiconductor device package are provided. The semiconductor device package includes a first substrate, a second substrate and an interconnection. The second substrate is arranged above the first substrate and has an opening. The interconnection passes through the opening and connects to the first substrate and the second substrate.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: November 12, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Chao Wei Liu
  • Semiconductor package structure and method for manufacturing the same
    Patent number: 12142576
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.
    Type: Grant
    Filed: March 14, 2023
    Date of Patent: November 12, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chun-Jun Zhuang
  • Semiconductor device package
    Patent number: 12142584
    Abstract: A semiconductor device package includes an electronic component and a substrate. The electronic component has a first surface and a second surface. The substrate is connected to the first surface of the electronic component through an adhesive layer. The substrate includes a first antenna disposed over the second surface of the electronic components through the adhesive layer.
    Type: Grant
    Filed: August 8, 2023
    Date of Patent: November 12, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • SEMICONDUCTOR SUBSTRATE AND PACKAGE STRUCTURE INCLUDING THE SAME
    Publication number: 20240373752
    Abstract: A semiconductor substrate and a package structure including the same are provided. The semiconductor substrate includes a first surface and a second surface. The first surface includes a filtering region. The second surface is opposite to the first surface and includes an amplifying region.
    Type: Application
    Filed: May 5, 2023
    Publication date: November 7, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Ting CHEN, Hung-Yi LIN, Cheng-Yuan KUNG
  • ELECTRONIC PACKAGE
    Publication number: 20240371739
    Abstract: An electronic package includes a pad, a dielectric layer, a bump, and a conductive element. The dielectric layer encapsulates the pad and includes an opening exposing the pad. The bump is disposed over the pad. The conductive element is disposed in the opening between the pad and the bump. The conductive element is configured to mitigate a shrinkage of an electrical path between the pad and the bump occupied by an expansion of the dielectric layer.
    Type: Application
    Filed: May 5, 2023
    Publication date: November 7, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Pin-Yao CHEN, Shiuan-Yu LIN, Hung-Jung TU
  • PACKAGE STRUCTURE
    Publication number: 20240371711
    Abstract: A package structure is provided. The package structure includes an amplifier and a filter structure. The amplifier has an active surface. The filter structure is disposed over the amplifier, and communicates with the amplifier through a first signal path substantially vertical to the active surface of the amplifier.
    Type: Application
    Filed: May 5, 2023
    Publication date: November 7, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Ting CHEN, Hung-Yi LIN, Cheng-Yuan KUNG