Abstract: The present invention facilitates efficient and effective device testing and debugging. In one embodiment, a tester system includes: a controller processor, a plurality of programmable accelerator circuits, and a plurality of load boards respectively. The plurality of programmable accelerator circuits providing input test signals and capture output test signals. The plurality of load boards apply the input test signals to a plurality of devices under test (DUTs) and capture the output test signals therefrom. In one exemplary implementation, each of the plurality of load boards includes a first set of connections that transmit input test signals to a respective DUT, a second set of connections that receive output test signals from the respective DUT, and sideband connectors. The sideband connectors receive test related information from the DUT.

Abstract: The invention concerns devices and methods for calibrating an Automated Test Equipment for automated testing of a Device Under Test. The method includes providing two digital channel signals by two different channels of the Automated Test Equipment, wherein the digital channel signals include an identical or a complementary pattern with respect to their edges. The method further includes sum-combining or difference-combining the two digital channel signals in order to obtain a combined residual signal. The step of combining is performed such that combining provides a combined residual signal without a time-variant component if the two digital channel signals have a predetermined time shift or a predetermined phase shift relative to each other, or such that the combined residual signal includes a time variant component if the two digital channel signals have a time shift different from the predetermined time shift or a phase shift different from the predetermined phase shift.

Abstract: A test apparatus for characterizing a device under test includes a test case generator, a test unit, a data storage unit, and a data analysis unit. The test case generator is configured to randomly generate a plurality of test cases, which include values of one or more input variables of a set of input variables. The test unit is configured to perform the plurality of test cases on the device under test. The data storage unit may store sets of test data, which are associated to the test cases and include values of input variables of a respective test case and corresponding values of output variables of the device under test related to the respective test case. The data analysis unit may further analyze the test data and is further configured to determine dependencies within a subset of variables of the test data to characterize the device under test.

Abstract: An electrical filter structure for forwarding an electrical signal from a first port to a second port in a frequency selective manner, wherein the filter is an edge-coupled filter, the filter comprising: a plurality of coupled line sections coupled in a series, comprising at least a first coupled line section and a last coupled line section; wherein the first port is connected with the first of the coupled line sections using a first transmission line; wherein the second port is connected with the last of the coupled line sections using a second transmission line; wherein the electrical filter comprises an open stub; wherein a length of the open stub is chosen such that an electrical length of the open stub is equal, within a tolerance of +/?20 percent, to a fourth of a wavelength of a signal having a frequency of twice a passband center frequency of the filter.

Abstract: An automated test equipment (ATE) system capable of performing a test of semiconductor devices is presented. The system comprises a first test board including a first FPGA communicatively coupled to a controller via an interface board, wherein the first FPGA comprises a first core programmed to implement a communication protocol, and further wherein the FPGA is programmed with at least one hardware accelerator circuit operable to internally generate commands and data for testing a DUT. The system also includes a second test board comprising a second FPGA communicatively coupled to the first test board, wherein the second FPGA comprises a second core programmed to implement a communication protocol for a device under test, wherein the second FPGA is further programmed to simulate a DUT, and wherein the first FPGA is operable to communicate with the second FPGA in order to test a communication link between the first test board and the second test board.

Abstract: A scalable test platform can include one or more of a plurality of different device interface boards and a plurality of primitives. The different device interface boards can be configured to provide a uniform interface to couple different types of DUTs and or DUTs with different form factors to the plurality of primitives. The plurality of primitives can be configured to distribute power to the DUTs, and to perform system level testing of the respective DUTs. The plurality of primitives can be configurable by a user to perform any number of system level tests on a number of different types of DUTs and or DUTs with different form factors.

Abstract: A signal processor is provided, comprising a data variable delay circuit that delays data signals, a clock variable delay circuit that delays a clock signal indicating timing to acquire the data signals, a jitter signal supplying unit that supplies, to the data variable delay circuit and the clock variable delay circuit, a jitter signal to change an amount of delay in a same direction, and a re-timing circuit that outputs a jitter-applied data signal obtained by re-timing the data signals delayed by the data variable delay circuit with the clock signal delayed by the clock variable delay circuit.

Abstract: The invention concerns a test program executor for an Automated Test Equipment, wherein the test program executor is configured to execute a test flow having a plurality of test suites, wherein the test program executor is configured to asynchronously execute the plurality of test suites, wherein a test suite contains a call of a function of a subsystem, wherein the function of the subsystem is related with a subsystem operation that is to be executed by the subsystem, and to signal a call of a function of a subsystem by transmitting an asynchronous request to the subsystem, the asynchronous request having a call-specific call tree hierarchy address and the call-specific operation to be executed by the subsystem, and wherein the test program executor is further configured to determine an execution order of the subsystem operations, such that the execution order of the subsystem operations depends on their call-specific call tree hierarchy addresses.

Abstract: An optical testing apparatus is used in testing an optical measuring instrument. The optical measuring instrument provides an incident light pulse from a light source to an incident object and receives a reflected light pulse as a result of reflection of the incident light pulse at the incident object. The optical testing apparatus includes two or more testing light sources, two or more optical penetration members, and a wave multiplexing section. The two or more testing light sources each output a testing light pulse. The two or more optical penetration members each have an optical penetration region and receive the testing light pulse from each of the two or more testing light sources for penetration through the optical penetration region. The wave multiplexing section multiplexes the testing light pulses penetrating through the two or more optical penetration members for provision to the optical measuring instrument.

Abstract: An automated test equipment (ATE) apparatus comprises a computer system comprising a system controller, wherein the system controller is communicatively coupled to a tester processor and an FPGA. The tester processor is operable to generate commands and data from instructions received from the system controller for coordinating testing of a device under test (DUT), wherein the DUT supports a plurality of non-standard sector sizes and a plurality of protection modes. The FPGA is communicatively coupled to the tester processor, wherein the FPGA comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing the DUT, and wherein the at least one hardware accelerator circuit is able to perform computations to calculate protection information associated with the plurality of protection modes and to generate repeatable test patterns sized to fit each of the plurality of non-standard sector sizes.

Abstract: A method for monitoring a communication link between a device under test (DUT) and automated test equipment is disclosed. The method comprises monitoring data traffic associated with testing a DUT using a protocol analyzer module, wherein the data traffic comprises a flow of traffic between the DUT and a protocol core of a programmable logic device, wherein the protocol analyzer module is integrated within the programmable logic device, wherein the programmable logic device is controlled by a system controller and is operable to generate commands and data to test the DUT, and wherein the protocol core is operable to generate signals to communicate with the DUT using a protocol associated with the DUT. The method further comprises saving results associated with the monitoring in a memory associated with the protocol analyzer module and transmitting the results upon request to an application program executing on the system controller.

Abstract: A method for monitoring communications between a device under test (DUT) and an automated test equipment (ATE) is disclosed. The method comprises programming an interface core and a protocol analyzer module onto a programmable logic device, wherein the programmable logic device is controlled by a system controller and is operable to generate commands and data to test a DUT, wherein the interface core is operable to generate signals to communicate with the DUT using a protocol associated with the DUT. The method also comprises monitoring data and command traffic associated with the protocol in the interface core using the protocol analyzer module and storing results associated with the monitoring in a memory comprised within the protocol analyzer module. The method finally comprises transmitting the results upon request to an application program associated with the protocol analyzer module executing on the system controller.

Abstract: Embodiments described herein perform incisions along the direction of the long axis of the waveguide, thereby exposing a trench structure which can be readily plated. Once divided and plated, the individual cut pieces can then be secured together to restore the original waveguide structure. In this fashion, multiple cut pieces can be secured together and used as “building blocks” to create a modular solution which can be used to provide a number of different customizable waveguide structures. Thus, embodiments described herein can perform plating procedures in a less expensive manner while achieving the benefits of ganged waveguide structures. Moreover, embodiments described herein can offer a modular approach to ganged waveguide design thereby allowing for end-user flexibility in testing.

Abstract: A load board to which a socket is mounted is electrically connected to a tester. The load board includes a first optical communication unit capable of transmitting and/or receiving signals by optical wireless communication with an electronic component handling apparatus that presses a DUT against the socket.

Abstract: A time measurement unit measures the time interval between edges to be monitored in a signal under test DUT_Output including serial data output from a device under test (DUT) 400. A comparison judgment unit calculates the number of bits of the serial data included between the edges to be monitored, based on the time interval thus measured. Furthermore, the comparison judgment unit compares the number of bits thus calculated with an expected value thereof.

Abstract: A method for diagnosing a root cause of failure using automated test equipment is disclosed. The method comprises monitoring data traffic associated with testing a device under test (DUT) in the automated test equipment using a plurality capture modules, wherein the plurality of capture modules are programmed onto a programmable logic device, wherein the programmable logic device is controlled by a system controller and is operable to generate commands and data to test the DUT, wherein the plurality of capture modules are operable to selectively capture the data traffic to be monitored, and wherein the data traffic monitored comprises a flow of traffic between the DUT and the system controller. The method further comprises saving results associated with the monitoring in respective memories associated with each of the plurality of capture modules. Further, the method comprises transmitting the results upon request to an application program executing on the system controller.

Abstract: Provided is a three-dimensional laminating and shaping apparatus 100 including a column unit 200 that is configured to output an electron beam EB and deflect the electron beam EB toward the front surface of a powder layer 32, an electron detector 72 that is configured to detect electrons that may be emitted in a predetermined direction from the front surface of the powder layer 32 when the powder layer 32 is irradiated with the electron beam EB, a melting judging unit 410 that is configured to generate a melting signal based on the strength of the detection signal from the electron detector 72, and a deflection controller 420 that is configured to receive the melting signal to determine the condition of the irradiation the electron beam.

Abstract: A measuring apparatus that measures a measurement target amount generated from a measurement target, includes an additional amount generating section, a sensor, and a deriving section. The additional amount generating section generates an additional amount to be added to the measurement target amount. The sensor measures a composite amount of the measurement target amount added with the additional amount. The deriving section derives the measurement target amount from an output of the sensor. The additional amount is a pulse. The pulse has an amplitude higher than the absolute value of the maximum of the measurement target amount. The maximum of the pulse is zero. The pulse has a frequency high enough to ignore the 1/f noise. The deriving section detects the output value of the sensor to derive the measurement target amount.

Abstract: An automated test equipment (ATE) system comprises a system controller, wherein the system controller is communicatively coupled to a tester processor and an FPGA. The FPGA is communicatively coupled to the tester processor, wherein the FPGA is configured to internally generate commands and data transparently from the tester processor for testing a DUT. Further, the system comprises a demultiplexer positioned between the DUT and the FPGA, wherein, responsive to a determination that the DUT is operating in a high speed mode, the demultiplexer is configured to channel data traffic from the DUT to a Serializer/Deserializer (SerDes) receiver on the FPGA, and further wherein, responsive to a determination that the DUT is operating in a low speed mode, the demultiplexer is configured to channel data traffic from the DUT to input buffers on the FPGA with switchable on/off input terminations.

Abstract: Fast parallel CRC determination to support SSD testing includes a test data pattern generator for generating test data for storage onto a memory storage device under test (DUT), wherein the generator is operable to generate, every clock cycle, a respective N bit word comprising a plurality of M bit subwords, a digest circuit operable to employ a digest function on each N bit word to produce, every clock cycle, a respective word digest for each N bit word, and a storage circuit operable to store each N bit word along with an associated word digest to the DUT.