Abstract: There is provided a magnetic noise rejection apparatus which includes: a plurality of cancellation coils arranged near a target object; a plurality of magnetic sensors disposed inside the respective cancellation coils; an adder circuit configured to take a sum of outputs of the plurality of magnetic sensors; and a feedback control circuit configured to supply the cancellation coils with such a common feedback drive current that the sum of the outputs of the magnetic sensors is equal to a sum of outputs of the magnetic sensors under a zero magnetic field.

Abstract: A measurement apparatus is provided that measures a current signal IDUT that flows through a device under test. A transimpedance amplifier converts the current signal IDUT into a voltage signal VOUT. A digitizer converts the voltage signal VOUT into digital data DOUT. A digital signal processing unit performs signal processing on the digital data DOUT, and controls the measurement apparatus. The measurement apparatus has a configuration comprising two separate modules, i.e., a probe module which is located in the vicinity of the device under test during a measurement, and a backend module connected to the probe module via at least one cable. The transimpedance amplifier is built into the probe module. The digitizer and the digital signal processing unit are built into the backend module.

Abstract: A heat exchanger which exchanges heat with a DUT while contacting the DUT includes: a heat exchange block which thermally contacts the DUT; a first heat transfer sheet which overlaps a front end surface of the heat exchange block; a second heat transfer sheet which overlaps the front end surface of the heat exchange block through the first heat transfer sheet; and a first holding member which holds the second heat transfer sheet.

Abstract: A method for performing a plurality of tests on a device under test comprises performing a plurality of tests on a device under test. Each test of the plurality of tests comprises a foreground process and a background process. The foreground process comprises a setup process during which a desired test mode is set. The background process comprises an upload process during which data captured from the device under test is provided. The foreground process is executed with a higher priority than the background process, thereby minimizing a delay between a start of consecutive tests of the device under test.

Abstract: A method for characterizing a FM chirp signal generated by a device under test (DUT) is disclosed. The method comprises receiving a selection of a sample frequency and chirp duration for capturing the FM chirp signal. The method also comprises down converting the FM chirp signal and capturing the FM chirp signal using a digital pin electronics card. The method comprises obtaining a plurality of period measurements from the captured FM chirp signal using a timing measurement unit (TMU) of an automated test equipment (ATE) and converting each of the plurality of period measurements into corresponding frequency values.

Abstract: Embodiments of the present disclosure utilize customizable waveguide fabrication technologies (e.g., 3D printer technology) and patch antenna arrays to create adaptable wave interfaces that can provide efficient signal routing for an ATE system. In this fashion, embodiments of the present disclosure allow for arbitrary waveguide routing from port to port and create high density port spacing at the PCB level and which specifically eliminates the large flange required of prior art waveguides. Furthermore, embodiments include the ability to integrate different waveguide components, including power splitters, couplers, terminations, etc., into a single structure. Thus, embodiments of the present disclosure can reduce signal path losses and simplify the mechanical construction of ATE systems while eliminating the need for coax cables and minimizing the length of PCB microstrips.

Abstract: An automated test equipment for simultaneous testing of multiple devices includes a traffic capture circuit configured to capture communications with a device under test, a capture memory configured to store the communications captured by the traffic capture circuit, and a routing logic configured to read the communications from the capture memory, e.g., random access memory (RAM). There may be one of each of the traffic capture circuit, the capture RAM, and the routing logic for each device of the multiple devices.

Abstract: Embodiments of the present disclosure use customizable waveguides that can be positioned next to each other in a structure that contains one single flange to provide a physical connection for the waveguides. In this fashion, many waveguides can be positioned within a small area to accommodate a tightly packed patch antenna array so that the waveguides can be positioned very close to the socket. As such, embodiments of the present disclosure allow more waveguides to be packed into a small area by providing a single structure that houses many waveguides and share only a single flange connection element that can be sized appropriately.

Abstract: A structure for performing socket power calibration comprises a plurality of socket ports on a load board electrically coupled to a plurality of traces on a first end of a flexible printed circuit board, wherein the plurality of traces are configured to allow traversal of an electrical signal from the plurality of socket ports to a waveguide. The structure further comprises the plurality of traces, wherein the traces are operable to terminate on a second end of the flexible printed circuit board into a plurality of patch antennas, wherein the plurality of patch antennas is adapted to radiate the electrical signal into the waveguide. Finally, the structure also comprises a power sensor electrically coupled to the waveguide, wherein the waveguide is configured to communicate the electrical signal from the waveguide to the power sensor.

Abstract: A method for characterizing a phase shifter in a device under test (DUT) using automated test equipment (ATE) is disclosed. The method comprises down converting an input signal received from the transmitter DUT to an intermediate frequency and routing the down converted input signal to a signal processor, wherein the signal processor generates I and Q signals using the input signal. The method further comprises setting an initial phase state on the phase shifter in the transmitter DUT and toggling at least one phase state bit to control the phase shifter to cycle through a plurality of phase states, wherein the changing phase states appear on the I and Q signals. Finally, the method comprises processing the I and Q signals to extract individual phase states programmed by the at least one phase state bit.

Abstract: A method of performing a test using automated test equipment (ATE) is disclosed. The method comprises configuring a proxy application programming interface (API) services module, wherein the proxy API services module provides an interface between a test framework and a test software environment, wherein the test framework communicates with the test software environment though the proxy API services module, wherein the test software environment is communicatively coupled with test hardware, and wherein the proxy API services module is configured to isolate the test framework from dependencies associated with the test software environment.

Abstract: A measuring apparatus that measures a measurement target amount generated from a measurement target, includes an additional amount generating section, a sensor, and a deriving section. The additional amount generating section generates an additional amount to be added to the measurement target amount. The sensor measures a composite amount of the measurement target amount added with the additional amount. The deriving section derives the measurement target amount from an output of the sensor. The additional amount is a pulse. The pulse has an amplitude higher than the absolute value of the maximum of the measurement target amount. The maximum of the pulse is zero. The pulse has a frequency high enough to ignore the 1/f noise. The deriving section detects the output value of the sensor to derive the measurement target amount.

Abstract: An electronic component handling apparatus (10) is provided which can improve the operation rate. The electronic component handling apparatus (10) includes: a contact arm (300) having a holding part (380) configured to hold a DUT (10A), the contact arm (300) being configured to press the DUT (10A) against a socket (410); an alignment device (200) including a camera (221) and a operation unit (230), the camera (221) being configured to image the DUT (10A) to acquire image information, the operation unit (230) being configured to adjust a position of the holding part (380) within a range of a maximum alignment amount (ALmax); and a control device (105) configured to control the contact arm (300) and the alignment device (200). When a predetermined condition is not satisfied, the control device (105) controls the contact arm (300) and the alignment device (200) so as to perform preliminary alignment work at least once.

Abstract: An apparatus for detecting an attitude of electronic components. The electronic components include an electronic component having a plurality of terminals. The apparatus includes a storage and an image processor. The image processor is configured to: extract a binarized image from an image acquired by an imaging device; perform image matching between a terminal in the binarized image and a terminal in a model image to extract attitude candidates of image matching; obtain coordinates of a corner part of the plurality of terminals from the binarized image of the electronic component; select an attitude candidate from among the attitude candidates of image matching; and output the attitude candidate as a detected attitude of the electronic component.

Abstract: Example features or aspects of the present invention are described in relation to a small, quiet integrated cooling system for an apparatus for testing electronic devices. Characteristics of the test apparatus including a low noise output, low power consumption and a compact size with a small spatial and volume footprint are selected for deployment and use in a an office like environment. The test apparatus comprises a chassis frame and a cooler frame disposed within the chassis frame and thus integrated within the test apparatus, which has a reduced form factor suitable for the in-office deployment. Embodiments offer the ability to maintain the working fluid at a constant temperature.

Abstract: An automated test equipment (ATE) apparatus is presented. The apparatus comprises a computer system comprising a system controller, wherein the system controller is communicatively coupled to a site module board comprising a tester processor and an FPGA wherein the system controller is operable to transmit instructions to the tester processor, and wherein the tester processor is operable to generate commands and data from the instructions for coordinating testing of a device under test (DUT) wherein the site module board comprises a compact form factor suitable for use during prototyping, and wherein the site module board is operable to be coupled with a DUT. Further, the FPGA is communicatively coupled to the tester processor, wherein the FPGA comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing the DUT.

Abstract: Embodiments provide a scheduler for scheduling test times of a plurality of tester software environments for an automatic test equipment. The scheduler is configured to automatically assign test times to the plurality of tester software environments, to acquire test instructions from a tester software environment of the plurality of tester software environments to which a current test time is assigned, to control the automatic test equipment to perform a test according to the test instructions in order to obtain test results, and to provide the test results to the tester software environment of the plurality of tester software environments to which the current test time is assigned.

Abstract: [Object] Provided is an electronic component handling apparatus capable of improving test quality. [Solving Means] An electronic component handling apparatus 20 handling a DUT 90 having a temperature detection circuit 92 and pressing the DUT 90 against a socket 11 electrically connected to a tester 10 includes: a temperature adjuster 40 adjusting a temperature of the DUT 90, a first receiver 51 receiving a first signal indicating a junction temperature Tj of the DUT 90 from the tester 10, a second receiver 52 receiving a second signal indicating a detection value Tj+c of the temperature detection circuit 92 from the tester 10, a first calculator 54 calculating a temperature Tj? of the DUT 90 by using the first signal and the second signal, and a temperature controller 55 controlling the temperature adjuster 40 on the basis of a calculation result of the first calculator 54.

Abstract: Presented embodiments facilitate efficient and effective access to a device under test. In one embodiment, a test system comprises: a device interface board (DIB) configured to interface with a device under test (DUT); and a primitive configured to control the device interface board and testing of the device under test. The primitive is an independent self contained test control unit comprising: a backplane interface configured to couple with the device interface board; a power supply component configured to control power to the backplane interface; and a site module configured to control testing signals sent to the device interface board and device under test. The site module is reconfigurable for different test protocols. The primitive can be compatible with a distributed testing infrastructure. In one exemplary implementation, the primitive and device interface board are portable an operable to perform independent testing unfettered by other control components.

Abstract: An automatic tuning assist circuit is coupled with a transmission antenna. Multiple switches SW and a first auxiliary capacitor CA are arranged between a first terminal and a second terminal of the automatic tuning assist circuit. A first control unit is configured to switch on and off the multiple switches SW in synchronization with a driving voltage VDRV. A power supply is configured to apply the driving voltage VDRV across a series circuit that comprises the transmission antenna and the automatic tuning assist circuit.