Abstract: In one embodiment, a semiconductor test control system includes a computer system having a plurality of hardware resources; a hypervisor installed on the computer system; and a test floor controller installed on the computer system. The hypervisor virtualizes the hardware resources and provides each of at least one virtual appliance with access to a respective virtual set of hardware resources. Each virtual set of hardware resources places its respective virtual appliance in controlling communication with at least a first aspect of a semiconductor test system, thereby enabling the respective virtual appliance to test a respective type of semiconductor device. The test floor controller is in controlling communication with i) at least a second aspect of the semiconductor test system, and ii) each of the at least one virtual appliance.

Abstract: A control device includes: a differential amplification circuit that amplifies a difference with respect to an input signal; and a clipping circuit that is connected to an output side of the differential amplification circuit and clips an input voltage. The differential amplification circuit includes a plurality of switching elements formed of a GaN semiconductor, and the clipping circuit includes a switching element formed of the GaN semiconductor.

Abstract: In one embodiment, a universal test container can include a universal external electrical interface configured to couple to each of a plurality of different devices to test. In addition, the universal test container is configured to enclose each of the plurality of different devices to test.

Abstract: Method and apparatus for performing Pattern-Controlled tests on an automatic test equipment (ATE). The ATE includes a diagnostic instrument and a control device. An application programming interface (API) is installed in the control device and operates to interact with a test program and thereby automatically controls the diagnostic instrument to perform a test. The test program is coded in a high-level programming language and defines a plurality of operation events for the test based on user input. The API identifies the operational events and determines respective operational types associated therewith. Events of an operational type are assigned to a respective pattern label. The pattern labels are then aggregated into a pattern burst which is downloaded to the diagnostic instrument.

Abstract: According to the present invention, a semiconductor device includes a semiconductor layer, a source electrode provided in the semiconductor layer, a drain electrode provided in the semiconductor layer and disposed away from the source electrode, a first gate electrode provided between the source electrode and the drain electrode and a second gate electrode provided between the source electrode and the drain electrode, the second gate electrode having at least a part thereof located closer to the drain electrode than the first gate electrode. The semiconductor layer includes a first facing part that is a part facing the first gate electrode; and a second facing part that is a part facing the second gate electrode. The first facing part does not conduct when a first gate voltage is 0 V or less. The second facing part does not conduct when a second gate voltage is 0 V or less.

Abstract: An instruction provider for providing a sequence of instructions based on a representation of a sequence of test vectors. Each instruction defines the provision of at least one test vector to a device under test. The instruction provider is configured to identify in the representation of the sequence of test vectors subsequences of test vectors which occur at least two times in the representation of the sequence of test vectors. Furthermore, the instruction provider is configured to store the identified subsequences in a dictionary memory structure and to provide the sequence of instructions such that the sequence of instructions includes at least a first instruction defining a first provision of a first subsequence of test vectors stored in the dictionary memory structure and a second instruction defining a second provision of the first subsequence. The first instruction and the second instruction reference to the same entry of the dictionary memory structure.

Abstract: Provided is an exposure apparatus that exposes a pattern on a sample, the exposure apparatus including a plurality of blanking electrodes that are provided corresponding to a plurality of charged particle beams and each switch whether the corresponding particle beam irradiates the sample according to an input voltage; an irradiation control section that outputs switching signals for switching blanking voltages supplied respectively to the blanking electrodes; and a measuring section that, for each blanking electrode, measures a delay amount that is from when the switching signal changes to when the blanking voltage changes.

Abstract: Disclosed herein is a scan optimizer system and method designed to generate optimal ATE input/output timing with small margin but yielding stable results. Therefore the scan test time is greatly improved.

Abstract: An automatic tuning assist circuit is coupled in series with a transmission antenna. A first switch and a second switch are arranged in series between a first terminal and a second terminal of the automatic tuning assist circuit. Furthermore, a third switch and a fourth switch are arranged in series between the first terminal and the second terminal. A first auxiliary capacitor is arranged between a connection node that connects the first switch and the second switch and a connection node that connects the third switch and the fourth switch. A control unit switches the first switch through the fourth switch with the same frequency as that of the driving voltage, and with a predetermined phase difference with respect to the driving voltage.

Abstract: Automated test equipment capable of performing a high-speed test of semiconductor devices is presented. The automated test equipment comprises a system controller for controlling a test program, wherein the system controller is coupled to a bus. The tester system further comprises a plurality of modules also coupled to the bus, where each module is operable to test a plurality of DUTs. Each of the modules comprises a tester processor coupled to the bus and a plurality of configurable blocks communicatively coupled to the tester processor. Each of the configurable blocks is operable to communicate with an associated DUT and further operable to be programmed with a communication protocol for communicating test data to and from said associated device under test.

Abstract: An automated test equipment for analyzing an analog time domain output signal of an electronic device under test includes: an analog-to-digital converter configured for converting an analog time domain signal; a sampling clock configured for producing a clock signal; a time-to-frequency converter configured for converting the digital time domain signal into a digital frequency domain signal so that the digital frequency domain signal is represented by frequency bins; a memory device configured for storing a set of empirically determined operating parameters; and a jitter components removal module for removing jitter components produced by the analog-to-digital converter, wherein the jitter removal module is configured for subtracting the lower spur and the upper spur of each frequency bin of the frequency bins from the digital frequency domain signal so that the cleaned digital frequency domain signal is produced.

Abstract: A reception circuit receives, via a cable, a transmission signal STX generated by a DUT. A comparator circuit compares a reception signal SRX after signal transmission with at least one threshold signal VTH, and generates a judgment value DOUT that represents a comparison result for every sampling timing. A threshold generation circuit generates at least one threshold signal VTH. A threshold control circuit adjusts each level of at least one threshold signal VTH at a given sampling timing based on the history of the judgment value DOUT acquired at a past sampling timing.

Abstract: In an embodiment, a universal test floor system includes a first robot that is configured to pack a plurality of universal test containers each including similar dimensions into a universal bin. Each universal test container is configured to enclose each of a plurality of different devices to test. The universal test floor system includes a universal conveyor configured to transport the universal bin. The first robot is configured to put the universal bin onto the universal conveyor and a second robot is configured to remove it. A universal test cell system is configured to receive the universal bin. The universal test cell system includes a plurality of test slots configured to receive a plurality of universal test containers. The universal test cell system is configured to test the plurality of different devices while each is located within one of the plurality of universal test containers.

Abstract: Embodiments of the present utilize a specialized modular load board in combination with previously-tested daughter boards to yield a final design for generating a new printed circuit board (PCB) for testing. Since the electrical characteristics of the daughter board are already known by the client and well established during previous testing procedures, similar test programs can be used for production-level testing that were used in client prototyping processes that involved the use of the previously-tested daughter board. Thus, embodiments of the present disclosure can use the features of the specialized modular load board and a client's tested daughter board to develop more reliable, production-ready circuits.

Abstract: Embodiments of the present disclosure include a modular load board or “frame” that contains a number of moveable connectors. The moveable connectors can be selectively displaced within the frame, as needed, to mate with test head pogo-pins and can be fixed in place on the frame using screws. Embodiments of the present disclosure provide multiple moveable sockets that can be positioned as needed within the frame so that a quick prototype modular load board can be designed and readily modified, if need be, without requiring hard wired traces within the PCB to connect the DUT socket to the test head interface regions. Using ribbon cables, embodiments of the present disclosure eliminate the need to have any hard wired traces within a PCB load board between the DUT socket and pogo pin interface blocks.

Abstract: A calibration module for a tester, for testing a device under test, includes a pair of RF-channel terminals, a calibration device, a pair of measurement terminals and a mode selector. The pair of RF-channels terminals is configured to send or receive measurement signals to or from an RF-channel of the tester. The calibration device is configured to perform a calibration of the RF-channel based on the measurement signals sent to, or received from, the RF-channel. The pair of measurement terminals is configured to send or receive measurement signals to or from the device under test. The mode selector is configured to connect, in a calibration phase, the pair or RF-channel terminals to the calibration device for calibrating the RF-channel and to connect, in a measurement phase, the pair of RF-channel terminals to the pair of measurement terminals for routing measurement signals from the RF-channel to the device under test or vice versa.

Abstract: A method for analyzing test results. The method includes selecting a first subset of tests from a plurality of tests. Test results are gathered from the plurality of tests in real-time. A first statistical analysis is performed on test results from the first subset of tests. At least one process control rule is initiated as determined by results of the first statistical analysis performed on the test results from the first subset of tests.

Abstract: A relay antenna includes a power relay coil. An automatic tuning assist circuit is coupled with the relay antenna. The automatic tuning assist circuit has first and second terminals coupled with the relay antenna. Multiple switches are arranged together with N (N represents an integer) auxiliary capacitors between the first terminal and the second terminal. A controller is configured to switch on and off each of the multiple switches in synchronization with an electric power signal transmitted from a wireless power supply apparatus.

Abstract: A test apparatus for generating reference scan chain test data comprises a test pattern generator and an output data modifier. The test pattern generator modifies a scan chain test input bit sequence by replacing a predefined number of start bits of the scan chain test input bit sequence by a predefined start bit sequence. Further, the test pattern generator provides the modified scan chain test input bit sequence to a device under test. The output data modifier modifies a scan chain test output bit sequence received from the device under test and caused by the modified scan chain test input bit sequence. The scan chain test output bit sequence is modified by replacing a predefined number of end bits of the scan chain test output bit sequence by a predefined end bit sequence to obtain the reference scan chain test data.