Abstract: A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. The integrated circuit structure includes a semiconductor layer with a major surface and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. The integrated circuit includes a capacitor having a bottom plate, dielectric layer and a top plate. In an associated method of manufacture, a first device region, is formed on a semiconductor layer. A field-effect transistor gate region is formed over the first device region. A capacitor comprising top and bottom layers and a dielectric layer is formed on the semiconductor layer.

Abstract: An apparatus and method for controlling the common mode voltage across a data storage device write head. The write current is supplied by a first plurality of parallel current sources each independently activated to limit the common mode voltage generated across the write head. A plurality of parallel resistive elements responsive to current supplied by a second plurality of parallel current sources bias an output transistor that further controls the write current. Each of the plurality of parallel resistive elements and each of the second plurality of parallel current sources is also independently activated to limiting the common mode voltage generated across the write head.

Abstract: A method of preventing formation of stringers adjacent a side of a CMOS gate stack during the deposition of mask and poly layers for the formation of a base and emitter of a bi-polar device on a CMOS integrated circuit wafer. The stringers are formed by incomplete removal of a hard mask layer over an emitter poly layer over a nitride mask layer. The method includes overetching the hard mask layer with a first etchant having a higher selectivity for the emitter poly material than for the material of the hard mask, determining an end point for the overetching step by detection of nitride in the etchant and applying a poly etchant that is selective with respect to nitride to remove any residual emitter poly.

Abstract: A method and apparatus are disclosed for improving the maximum data rate of reduced-state Viterbi detectors with local feedback in magnetic recording systems. A read channel signal is processed in a magnetic recording device by precomputing branch metrics, intersymbol interference estimates or intersymbol interference-free signal estimates for speculative sequences of one or more channel symbols; selecting one of the precomputed values based on at least one decision from at least one corresponding state; and selecting a path having a best path metric for a given state.

Abstract: A voltage regulator, a method of regulating voltage and an IC including a voltage regulator. In one embodiment, the voltage regulator includes: (1) a DC precision amplifier configured to generate a DC precision signal based on a reference voltage and a regulated output of the voltage regulator and (2) a response amplifier, coupled in parallel with the DC precision amplifier, configured to generate an error signal based on the reference voltage and the regulated output, the response amplifier further configured to generate the regulated output based on a regulating signal comprised of the error signal and the DC precision signal. The DC precision amplifier may be a CMOS amplifier and the response amplifier may be a NPN amplifier.

Abstract: An SDARS receiver includes an analog front end configured to receive a composite signal. An A/D converter is coupled to the analog front end and converts the signal to a digitized signal. A digital down converter (DDC) is coupled to the A/D converter and down converts the digitized signal to a down converted signal. A demodulator demodulates the down converted signal. The receiver includes a digital automatic gain control (DAGC) coupled to an output of the A/D converter and before the demodulator. An automatic gain controller is coupled to the DAGC for providing an automatic gain control signal.

Abstract: An ADC circuit includes multiple comparators and a controller coupled to the comparators. Each of the comparators is operative to generate an output indicative of a difference between a first signal representative of an input signal applied to the ADC circuit and a corresponding reference signal. The controller is operative to perform at least one of: (i) activating a subset of the comparators during a given sample period being; and (ii) controlling levels of the corresponding reference signals of the comparators as a function of a level of the input signal. A number of active comparators during the given sample period is no greater than one less than a number of regions into which the input signal is quantized.

Abstract: An offset history table is implemented and maintained in a BLUETOOTH device and is used to pre-seed an expected frequency offset of a received signal from another BLUETOOTH device. The disclosed offset history table includes one entry for each piconet device in a particular piconet, each entry including a best guess of the relevant piconet device's frequency offset with respect to the receiving BLUETOOTH device. Using a frequency offset history table and a pre-seeded frequency offset corresponding to an expected frequency offset based on the offset value maintained in the frequency offset history table, the performance of a BLUETOOTH device can be increased in a steady state piconet scenario.

Abstract: Disclosed is a circuit that adjusts a characteristic of a signal transmitted from a transmitter to a receiver over a communication channel (e.g., a wire, a backplane, etc.). The circuit includes a latch that receives the signal at a predetermined point in the circuit and samples a voltage of the signal many times after a threshold voltage is applied to the latch. The circuit also includes a processor that determines the characteristic of the signal when the sampled voltages indicate a transition point and that adjusts the threshold voltage when the sampled voltages do not indicate a transition point. The processor adjusts the characteristic of the signal by adjusting at least one of a current and a voltage of the transmitter when the characteristic of the signal is outside a predetermined range.

Abstract: A low-latency, peer-to-peer TDM bus including one or more data lines and one or more control lines is provided. Attached devices access the bus sequentially in order of their bus addresses. During a device's access period, if the device has data to transmit, the device places its address on the data lines, asserts a START signal on the bus, and proceeds to transmit data to the other devices on the bus. When the data transmission is completed, the device asserts an END signal on the bus, thus passing control of the bus to the next device in the sequence. If the device has no data to transmit, the device simply places its address on the data lines, asserts the START signal, and asserts the END signal, and control passes directly to the next device in line. In this manner, each device has an opportunity to transmit on the bus.

Abstract: A cache memory architecture, a method of operating a cache memory and a memory controller. In one embodiment, the cache memory architecture includes: (1) a segment memory configured to contain at least one most significant bit (MSB) of a main memory address, the at least one MSB being common to addresses in a particular main memory logical segment that includes the main memory address, (2) a tag memory configured to contain tags that include other bits of the main memory address and (3) combinatorial logic associated with the segment memory and the tag memory and configured to indicate a cache hit only when both the at least one most significant bit and the other bits match a requested main memory address.

Abstract: An apparatus and method for determining a head parameter value (e.g., head resistance) of a resistive head. A test head current is supplied to the head during a head parameter measurement interval using the same current sources that supply a bias current to the head during an operating (read operation) interval. The determined head parameter value is latched for use in setting the control loop gain for a control loop that controls the current sources during the operating interval.

Abstract: Part of the spectrum of two or more input signals is encoded using conventional coding techniques, while encoding the rest of the spectrum using binaural cue coding (BCC). In BCC coding, spectral components of the input signals are downmixed and BCC parameters (e.g., inter-channel level and/or time differences) are generated. In a stereo implementation, after converting the left and right channels to the frequency domain, pairs of left- and right-channel spectral components are downmixed to mono. The mono components are then converted back to the time domain, along with those left- and right-channel spectral components that were not downmixed, to form hybrid stereo signals, which can then be encoded using conventional coding techniques. For playback, the encoded bitstream is decoded using conventional decoding techniques. BCC synthesis techniques may then apply the BCC parameters to synthesize an auditory scene based on the mono components as well as the unmixed stereo components.

Abstract: Methods and apparatus are provided for data rate detection using a data eye monitor. The data rate is one of a plurality of data rates comprising a base rate and one or more divide-by-N multiples of the base rate, where N is an integer. The data rate of a received signal is detected by sampling the received signal; comparing the samples for a plurality of full rate data eyes associated with the received signal to determine if there is a mismatch between at least two predefined samples; and detecting the data rate by evaluating the comparison based on predefined criteria. The comparison can be performed by an exclusive or (XOR) logic gate for samples of at least two adjacent data eyes of a given rate.

Abstract: Various approaches to recover data are described. An one example, an encoded data stream is processed in a first channel decoder producing a channel decoder output. The channel decoder output and the encoded data stream are processed in an error compensation unit to compensate the channel decoder output for low frequency noise and produce an error compensated data stream. The error compensated data stream is processed in a second channel decoder to produce a recovered data stream, wherein the recovered data stream has a reduction in the number of errors as compared to the encoded data stream. Systems to iteratively recover data from an encoded data stream are also described.

Abstract: The invention is a method and apparatus for frequency-domain adaptive filtering that has broad applications such as to equalizers, but is particularly suitable for use in acoustic echo cancellation circuits for stereophonic and other multiple channel teleconferencing systems. The method and apparatus utilizes a frequency-domain recursive least squares criterion that minimizes the error signal in the frequency-domain. In order to reduce the complexity of the algorithm, a constraint is removed resulting in an unconstrained frequency-domain recursive least mean squares method and apparatus. A method and apparatus for selecting an optimal adaptation step for the UFLMS is disclosed. The method and apparatus is generalized to the multiple channel case and exploits the cross-power spectra among all of the channels.

Abstract: A passive mixer includes a transconductance amplifier having a source degeneration capacitance. The transconductance amplifier has an input for receiving an input signal and an output for outputting a current signal. A multiplier is provided for mixing a local oscillator signal with the current signal so as to provide an output signal at an output of the passive mixer. A capacitive load is connected to the output of the passive mixer.

Abstract: An integrated circuit device for use in a node of a communication system is provided. The integrated circuit device includes a memory configured to store data written thereto by a receiver associated with the node in accordance with a receiver clock, and to read data therefrom by a transmitter associated with the node in accordance with a transmitter clock. The integrated circuit device also includes a control logic circuit that is in communication with the memory, and is configured to send a control signal to the transmitter to adjust a speed of the transmitter clock responsive to an operating condition of the memory.

Abstract: A network processor or other type of processor includes an interface comprising a plurality of signal lines, and interface circuitry adapted to receive clock signals for respective interface clock domains of the processor. The interface circuitry comprises a plurality of sampling registers clocked by respective ones of the clock signals. The interface circuitry is configurable in a variety of different configurations, each providing a different association between designated subsets of the signal lines and the clock domains of the processor.

Abstract: In one embodiment, the invention is an apparatus (e.g., an Ethernet switch) having an isolated side and a line side. A line-side connector is connectable to a cable. An isolated-side physical-layer module (1) is electrically coupled to the connector via a signal-isolation transformer and (2) processes signals transmitted over the cable. A line-side power conditioning module (1) is electrically coupled to an isolated-side power switcher via a power-isolation transformer that converts an AC power signal received from the power switcher into a transformed AC power signal and (2) converts the transformed AC power signal into a cable power signal to be supplied via the connector to the cable in order to power a cable-powered device connected to the cable. An isolated-side control module performs a detection function in which the control module determines whether or not a cable-powered device is connected to the cable.