Abstract: A method for forming a germanium-enriched region in a heterojunction bipolar transistor and a heterojunction bipolar transistor comprising a germanium-enriched region. A base having a silicon-germanium portion is formed over a collector. Thermal oxidation of the base causes a germanium-enriched region to form on a surface of the silicon-germanium portion subjected to the thermal oxidation. An emitter is formed overlying the germanium-enriched portion region. The germanium-enriched region imparts advantageous operating properties to the heterojunction bipolar transistor, including improved high-frequency/high-speed operation.

Abstract: The present invention implements an apparatus for calibrating a phase locked loop (PLL) circuit. The apparatus includes a detector for detecting frequencies of a reference signal and a controlled oscillator contained in the PLL circuit. The detector outputs the frequency difference to a control circuit. The control circuit is programmed to adjust one or more control signals to the controlled oscillator based upon the frequency difference in an orderly fashion to complete the calibration process.

Abstract: Methods and apparatus are provided for determining the threshold position of one or more latches employed for decision-feedback equalization. A threshold position of a latch employed by a decision-feedback equalizer is determined by constraining input data such that the input data only contains transitions from a first binary value; obtaining a plurality of samples of a single-sided data eye associated with the constrained input data; and determining a threshold position of the latch based on the samples. The constrained input data can comprise (i) transitions from a binary value of 1 to a binary value of 0 or 1; or (ii) transitions from a binary value of 0 to a binary value of 0 or 1. The size of the single-sided data eye can be obtained by analyzing a histogram associated with the single-sided data eye to identify a region having a constant hit count.

Abstract: Various systems and methods for error reduction in a digital information system are disclosed herein. As one example, a digital storage system is provided that includes a soft output Viterbi algorithm channel detector operable to receive an encoded data set, and to provide a hard and a soft output representing the encoded data set. The hard and the soft output from the soft output Viterbi algorithm channel detector are provided to a single parity row decoder that provides another hard output that is an error reduced representation of the encoded data set. The encoded data set is additionally provided from the buffer to another channel detector via a delay element. The hard output from the single parity row decoder and the time shifted encoded data set are provided to coincident with each other to another channel detector.

Abstract: Various systems and methods for implementing multi-mode semiconductor devices are discussed herein. For example, a multi-mode semiconductor device is disclosed that includes a device package with a number of package pins. In addition, the device includes a semiconductor die or substrate with at least two IO buffers. One of the IO buffers is located a distance from a package pin and another of the IO buffers is located another distance from the package pin. One of the IO buffers includes first bond pad electrically coupled to a circuit implementing a first interface type and a floating bond pad, and the other IO buffer includes a second bond pad electrically coupled to a circuit implementing a second interface type. In some cases, the floating bond pad is electrically coupled to the circuit implementing the second interface type via a conductive interconnect, and the floating bond pad is electrically coupled to the package pin.

Abstract: A power switching circuit is provided for use in an integrated circuit including at least a first voltage rail and a second voltage rail. The power switching circuit includes at least one MOS device having a first source/drain adapted for connection to the first voltage rail, a second source/drain adapted for connection to the second voltage rail, and a gate adapted for receiving a control signal. The MOS device selectively connects the first voltage rail to the second voltage rail in response to the control signal. The first and second voltage rails form a grid overlying the power switching circuit, the first and second voltage rails being formed in different planes relative to one another. The connection between the power switching circuit and the first voltage rail is made at an interface between the first and voltage rails.

Abstract: A modem uses information from prior calls in a current call if the current communication line is similar to the communication line of a prior call. During modem training, the current communication line is compared to a communication line used during at least one prior call. If the characteristics are substantially similar, stored data mode information from the prior call(s) is used to design a signal constellation for use during the current call's data mode. If the number of prior calls exceeds a value, then the signal constellation may be designed using previously stored data mode information without using information from the current call's training mode. If the number of prior calls does not exceed the value, then the signal constellation may be designed using the previously stored data mode information and information from the current call's training mode.

Abstract: Various embodiments of the present invention provide systems and circuits for clock signal generation. For example, various embodiments of the present invention provide semiconductor devices that include a power source and a phase lock loop circuit. The power source provides a supply voltage to the phase lock loop circuit. The phase lock loop circuit includes and on-chip control voltage source and a voltage controlled oscillator. The on-chip control voltage source is capable of producing a control voltage that varies between a minimum voltage and a maximum voltage. The voltage controlled oscillator receives the control voltage and provides a clock signal with a frequency corresponding to the control voltage. The maximum voltage is greater than the supply voltage. For example, in some embodiments of the present invention, the maximum voltage is more than double the supply voltage. As another example, in some embodiments of the present invention, the maximum voltage is more than six times the supply voltage.

Abstract: Methods and apparatus for synchronizing a first clock of a transmit node and a second clock of a receive node in a packet network are provided. Receive time stamps are generated for transferred packets at a receive node in-accordance with the second clock. Propagation delay variation is filtered from receive time stamp intervals through a filter in accordance with a frequency of the second clock. The filtered receive time stamp intervals and transmit time stamp intervals of the transferred packets are input into a phase locked loop to generate a new frequency for the second clock. The filter and the second clock are updated in accordance with the new frequency for synchronization with the first clock of the transfer node.

Abstract: A two-step ADC is provided that achieves significant improvements in the settling time window available for CDAC conversion, FADC sub-ranging and FADC conversion without increasing the amount of chip area or power that are consumed by the ADC. The ADC uses interleaved sampler/buffer circuits to sample the incoming analog signal on different phases of the clock signal. MUXes provide the samples obtained by the sampler/buffer circuits to the CADC and FADC circuits in ping pong fashion in such a way that the CADC and FADC circuits are converting during every clock period. In addition, these improvements are achieved without increasing the number of potential sources of bit decision mismatches in the two-step sub-ranging ADC.

Abstract: The invention, in one aspect, provides a semiconductor device that comprises a collector located in a semiconductor substrate and an isolation region located under the collector, wherein a peak dopant concentration of the isolation region is separated from a peak dopant concentration of the collector that ranges from about 0.9 microns to about 2.0 microns.

Abstract: Methods and apparatus are provided for reducing disk seek time to improve the overall throughput by improving the scheduling of read requests. One or more requests to read data from one or more disks are scheduled by suspending one or more requests to read data from the disk for a predefined period of time. The read suspension can be initiated, for example, in response to a request to read data from the disk, such as a speculative read operation. The predefined period of time may be approximately equal, for example, to an expected duration of the read request operation, an expected seek time, a predefined recovery time or a time since a last request less a recovery time. The read suspension can be conditioned upon one or more predefined criteria, such as a disk bandwidth threshold being satisfied, a time since a last request threshold being satisfied and a condition that only a request for a different stream than a currently requested stream is suspended.

Abstract: A despreader for generating one or more despread values corresponding to application of one or more despreading codes to a sequence of spread values comprises a data buffer, an adder, a subtractor, and a controller. The adder is adapted to generate a sum of a pair of values read from the data buffer. The subtractor is adapted to generate a difference of the pair of values read from the data buffer. The controller is adapted to control (1) reading of the pair of values from the data buffer and (2) writing of the sum and difference values into the data buffer. After each pair of spread values is stored in the data buffer, the despreader generates and stores one or more pairs of sum and difference values in the data buffer.

Abstract: An integrated circuit having an integrated circuit die and at least one height-sensing pad disposed on a top surface of the integrated circuit die and electrically isolated from the die circuitry. At least one bond pad is disposed on a top surface of the integrated circuit die and electrically connected to the die circuitry. The at least one bond pad is configured for wire-bonding to a lead of a leadframe utilizing a height coordinate of the at least one height-sensing pad.

Abstract: In training a SERDES, a Common Electrical Interface (CEI) training frame, having certain bits of information embedded therein, is transmitted over a path which comprises transmitter, channel, and receiver components. The present invention analyzes the resulting received signal and determines the effective aggregate channel impulse response of these three components. The invention then determines an estimate of the inverse of this aggregate channel and uses this determination to reduce distortions that have been introduced into a signal that has been transmitted over the path.

Abstract: Various systems and methods for low power multi-rate data paths are disclosed. As one example, a semiconductor device that includes a multi-rate data path is discussed. The multi-rate data path includes at least two register circuits with an output of one of the register circuits electrically coupled to an input of the other register circuit via a combinational logic block. In addition, the semiconductor device includes a control circuit that is operable to modify the rate at which the multi-rate data path operates by selectably bypassing at least one of the register circuits.

Abstract: Various systems and methods for generating error indications are disclosed herein. In some cases, the error indication is used as an erasure pointer in a memory access system. As one particular example, a system for generating an erasure pointer is disclosed that includes accumulating a number of error values into an overall error value, and comparing the overall error value to an error threshold. When the overall error value exceeds the error threshold, an erasure pointer is generated. In one particular case, the error values are derived from a look up table using thermometer codes generated by an analog to digital converter. In other cases, the error values are derived from comparing a soft output with a reliability threshold.

Abstract: A method and apparatus for selecting and mixing electronic signals. The circuit has an operational amplifier and two or more ganged, tapped-resistors in which the tap divides the resistance into a first and a second resistance. The tapped-resistors are connected so that either the first or the second resistance provides the effective input resistance for that signal at the operational amplifier. The second resistance of one of the tapped-resistors provides the output resistance for all signals at operational amplifier. As the tapped resistors are equivalent and their taps ganged, when the signals are mixed, those signals whose effective input resistance at the operational amplifier is selected to be the second resistance have unit gain, while those signals whose effective input resistance at the operational amplifier is selected to be the first resistance have a gain equal to the second resistance divide by the first resistance.

Abstract: Methods and apparatus are disclosed for DC offset estimation and for DC offset compensation that collectively reduce or eliminate the distortion of subcarriers due to DC offset in an OFDM receiver. The DC offset estimation is obtained by subtracting a sum of time domain samples of an OFDM symbol for two consecutive OFDM symbols or subtracting a known transmitted OFDM symbol and a frequency domain representation of a received version of the known OFDM symbol (at least one of which is adjusted to compensate for channel distortion). The DC offset compensation is accomplished by removing the estimated DC offset from the received signal. The DC estimation process and the DC compensation process can be connected in disclosed feed-forward or feedback configurations.

Abstract: A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. The integrated circuit structure includes a semiconductor layer with a major surface and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. The integrated circuit includes a capacitor having a bottom plate, dielectric layer and a top plate. In an associated method of manufacture, a first device region, is formed on a semiconductor layer. A field-effect transistor gate region is formed over the first device region. A capacitor comprising top and bottom layers and a dielectric layer is formed on the semiconductor layer.