Abstract: A feedback cancellation assembly for an electroacoustic communication apparatus may include a signal transmission path for generation and emission of an outgoing sound signal to an external environment through an electrodynamic loudspeaker and a signal reception path comprising a microphone for generation of a microphone input signal corresponding to sound received from the external environment. The signal reception path may generate a digital microphone signal. The outgoing sound signal may be acoustically coupled to the microphone. An electronic feedback cancellation path may be coupled between a tapping node and a summing node to produce a feedback cancellation signal to the summing node.

Abstract: This application discusses, among other things apparatus and methods for a voltage boost circuit. In an example, a voltage boost circuit can include first and second inverters, sharing a first supply node, and sharing a second supply node, a first charge transfer capacitor, configured to couple a first clock signal to the first inverter output, a second charge transfer capacitor, configured to couple a second clock signal to the second inverter output, the second clock signal being out-of-phase with the first clock signal, a first gate drive capacitor, configured to couple the first clock signal to the second inverter input, and a second gate drive capacitor, configured to couple the second clock signal to the first inverter input.

Abstract: A system may include a detector, a controller, a shuffler, and a processor. The detector may detect a signal. The controller may control the shuffler based upon the signal. The shuffler may shuffle a plurality of channels at the input of a plurality of processing elements of the processor based upon the signal. The processor may process the signal according to the plurality of channels as configured by the shuffler.

Abstract: The present invention relates in one aspect to a voice coil temperature protector for electrodynamic loudspeakers. The voice coil temperature protector comprises an audio signal input for receipt of an audio signal supplied by an audio signal source and a probe signal source for generation of a low-frequency probe signal. A signal combiner is configured to combine the audio signal with the low-frequency probe signal to provide a composite loudspeaker drive signal comprising an audio signal component and a probe signal component. The voice coil temperature protector comprises a current detector configured for detecting a level of a probe current component flowing through the voice coil in response to the composite loudspeaker drive signal and a current comparator which is configured to comparing the detected level of the probe current component with a predetermined probe current threshold.

Abstract: A signal gate is provided where the gate can be low impedance to allow a signal to pass or be high impedance to block it. The signal gate has two output nodes arranged such that during the blocking mode spurious signals passing through the gate by way of parasitic components are presented as common mode signals at the output nodes.

Abstract: A wireless network element is operably couplable to an antenna array for communicating with at least one remote wireless communication unit. The antenna array comprises a plurality of radiating elements where at least one first radiating element of the plurality of radiating elements is arranged to create a radiation pattern in a sector of a communication cell. The wireless network element comprises a receiver arranged to receive and process at least one signal from the at least one remote wireless communication unit via the at least one first radiating element. The wireless network element also comprises a beam scanning module for stepping/sweeping the radiation pattern through the sector of the communication cell, such that at least one signal from the at least one remote wireless communication unit is processed to identify signal parameters representative of incoming signal power and angle of arrival of the received at least one signal.

Abstract: A power supply monitoring circuit for monitoring a voltage at a power supply node compared to a reference node, the power supply monitoring circuit comprising a first field effect transistor and first and second voltage dropping components arranged in current flow communication between the power supply node and the reference node and each having first and second nodes, and wherein a first node of the first voltage dropping component is connected to one of the first and second nodes of the field effect transistor, and a gate of the field effect transistor is connected to the second node of the first voltage dropping component, and an output signal is taken from a connection made with the first field effect transistor.

Abstract: Existing synchronization methods can be inefficient in hardware-assisted implementations because of the effects of various jittery events. Thus, a method and an apparatus are provided to synchronize a slave device's clock to a master device's clock for a hardware-assisted implementation. The method can include the receipt of three messages. Time differences are determined based on a time extracted from two of the messages and a time of receipt of a different one of the messages. The slave device's clock can be adjusted based on these time differences. Thus, this method, which can include a dynamic weighted average to compute and implement the synchronization, can synchronize the clock of the slave device to the clock of the master device in a faster time interval.

Abstract: A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal.

Abstract: The present invention relates in one aspect to a DC linear voltage regulator circuit for generating a regulated DC output voltage based on a DC input voltage. The DC linear voltage regulator circuit comprises a DMOS pass transistor comprising drain, gate, source and bulk terminals wherein the drain terminal is connected to a regulator output which is configured to supply the regulated DC output voltage and the source terminal is connected to a regulator input for receipt of the DC input voltage. The DC linear voltage regulator circuit comprises a switchable leakage prevention circuit, connected to the bulk terminal of the DMOS pass transistor, and configured to automatically detect and interrupt a flow of leakage current from the regulator output to the bulk terminal.

Abstract: A system, such as a system-on-chip, has a non-debug domain and a debug domain. The debug domain has a debug framework that enables a debugger driven, non-debug domain system reset. The system includes a reset control unit, and a debug trigger mechanism that includes a debug trigger interface (DTI) connected to the reset control unit. The DTI is configured to trigger the reset control unit to reset the non-debug domain. The DTI may further be configured to monitor a status of the non-debug domain system reset.

Abstract: A serial peripheral interface (SPI) host port is disclosed that enables a host external to a processor to access the processor's memory-mapped resources using SPI memory command protocol. An exemplary processor can include a system interconnect connected to memory-mapped resources and a SPI host port connected to the system interconnect. The SPI host port is configured to use SPI memory command protocol to access memory-mapped resources of the processor for the host external to the processor.

Abstract: The present disclosure provides a feedback control system and method for a bidirectional VCM. The system employs an analog core that is common to both the PWM and linear modes of operation. The analog core includes a feedback mechanism that determines the error in the current flowing through the motor. The feedback mechanism produces an error voltage that corresponds to the current error, and applies the voltage to a control driver. The control driver then controls the motor, based on the error voltage, in either a PWM or linear mode. By sharing a common core, the switching time between modes is improved. Furthermore, the output current error between modes is reduced.

Abstract: Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL's division value. The reset phase adjustment calculator can include a counter for counting a number of cycles of the reference clock signal since initialization of the fractional-N synthesizer, and the reset phase adjustment calculator can generate a phase adjustment signal based on the count. The synchronization circuit can synchronize the PLL in response to a synchronization signal, and can correct for a synchronization phase error indicated by the phase adjustment signal.

Abstract: A sigma-delta modulator circuit selectively removes a dither signal previously added to an input of a quantizer circuit from the quantizer circuit output when addition of the dither signal causes a digital state change in the quantizer circuit output. Various examples for enabling the selective removal of the dither signal are described. In one embodiment, a second quantizer circuit provides a non-dithered output signal for comparison, by a digital comparator, with the dithered output signal. In another embodiment, a single quantizer circuit provides the dithered and non-dithered output signals in turn, for comparison. A subtraction circuit may remove the dither signal as appropriate. Embodiments enable retention of the improved limit cycle tone reduction achievable via dithering while reducing the need for circuits with increased signal headroom, and associated design complexity and power dissipation.

Abstract: A signal processing apparatus that includes a circuit in which a signal processing function is performed during a first time period, the signal processing apparatus including or being associated with a switch or a filter in a power supply to the signal processing apparatus so as to disconnect the signal processing apparatus from the power supply or to filter the power supply during a second time period that is coincident with at least part of the first time period.

Abstract: A system for receiving at least two data streams and providing a single input data stream to a MIPI's CSI Tx is disclosed. The two received data streams are written into respective data buffers. The system includes a control logic configured to control reading of data stored in the buffers to a multiplexer, the read-side clock being a multiple of a frequency of a fixed frequency clock. The control logic is further configured to control the multiplexer to combine data read from each buffer that corresponds to a complete unit of data into a separate portion and multiplex the separate portions into the input data stream. In this manner, two data streams may be transmitted using a single CSI Tx. When the two data streams are received by the system from an APIX interface, the system provides a bridge between the APIX interface and MIPI's CSI Tx.

Abstract: A protection device is provided that exhibits a turn on time of order of one nanosecond or less. Such a device provides enhanced protection for integrated circuits against electrostatic discharge events. This in turn reduces the risk of device failure in use. The protection device can include a bipolar transistor structure connected between a node to be protected and a discharge path.

Abstract: A magnetic core is provided for an integrated circuit, the magnetic core comprising: a plurality of layers of magnetically functional material; a plurality of layers of a first insulating material; and at least one layer of an secondary insulating material; wherein layers of the first insulating material are interposed between layers of the magnetically functional material to form subsections of the magnetic core, and the at least one layer of second insulating material is interposed between adjacent subsections.

Abstract: Apparatus and methods for frequency lock enhancement of phase-locked loops (PLLs) are provided. In one aspect, a PLL can include a VCO having a tuning voltage input and a frequency tuning circuit configured to set a frequency band setting of the VCO. The frequency tuning circuit can include a voltage monitor configured to compare the voltage level of the tuning voltage input to one or more tuning voltage threshold levels, a control circuit configured to control at least a frequency band setting and a bias current setting of the VCO, and an amplitude detection circuit configured to compare an amplitude of an oscillation signal of the VCO to one or more amplitude threshold levels.