Patents Assigned to Analog Devices Global
  • Transducer amplification circuit
    Patent number: 9479865
    Abstract: A transducer amplification circuit may include a preamplifier circuit with a signal input receiving a transducer signal to provide an amplified transducer signal comprising audible frequency components and ultrasonic frequency components. The transducer amplification circuit may include a first sigma-delta modulator configured to sample and quantize the amplified transducer signal to generate a first digital transducer signal comprising a first quantization noise signal. The first sigma-delta modulator may include a first noise transfer function having a high pass response in at least a portion of an audible frequency range to push the quantization noise signal to ultrasonic frequencies. A second sigma-delta modulator is configured to sample and quantize the amplified transducer signal to generate a second digital transducer signal comprising a second quantization noise signal.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: October 25, 2016
    Assignee: Analog Devices Global
    Inventors: Khiem Quang Nguyen, Kim Spetzler Berthelsen, Robert Adams
  • Phase corrector for laser trimming, an integrated circuit including such a phase corrector, and a method of providing phase correction in an integrated circuit
    Patent number: 9478359
    Abstract: A phase corrector for laser trimming a component, the phase corrector comprising: a first correction structure located to a first side of the component, the first correction structure comprising first and second correction regions at first and second distances from the component; and a second correction structure located to a second side the component, the second correction structure comprising third and fourth correction regions at third and fourth distances from the component.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: October 25, 2016
    Assignee: Analog Devices Global
    Inventors: Bernard Patrick Stenson, Paul Martin Lambkin, Colette J. Blaney, John Beatty
  • Two-axis vertical mount package assembly
    Patent number: 9475694
    Abstract: Vertical mount package assemblies and methods for making the same are disclosed. A method for manufacturing a vertical mount package assembly includes providing a base substrate having electrical connections for affixing to external circuitry, and providing a package having a mounting region configured to receive a device therein. Flexible electrical leads are formed between the base substrate and the package. The flexible leads can include a plurality of aligned grooves to guide bending. After forming the flexible electrical leads, the package is rotated relative to the base substrate. The aligned grooves can constrain the relative positions of the substrates during rotation, and the beveled edges of the base substrate and package can maintain a desired angular relationship (e.g., perpendicular) between the base substrate and the package after rotation.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: October 25, 2016
    Assignee: ANALOG DEVICES GLOBAL
    Inventors: Arturo Martizon, Jr., Thomas M. Goida
  • Localized strain relief for an integrated circuit
    Patent number: 9466666
    Abstract: An integrated circuit may include a semiconductor die having a trench formed in a surface of the semiconductor die. One or more circuit components may be formed on the surface of the semiconductor die. The trench can extend into the semiconductor die next to at least one circuit component. The trench may surround the circuit component partially or wholly. The trench may be filled with a material having a lower bulk modulus than the semiconductor die in which the trench is formed.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: October 11, 2016
    Assignee: ANALOG DEVICES GLOBAL
    Inventors: Patrick F. M. Poucher, Padraig L. Fitzgerald, John Jude O'Donnell, Oliver J. Kierse, Denis M. O'Connor
  • Apparatus and methods for using tuning information to adaptively and dynamically modify the parameters of an RF signal chain
    Patent number: 9467151
    Abstract: Provided herein are apparatus and methods for using tuning information to adaptively and dynamically modify the parameters of an RF signal chain. The tuning information from an oscillator core, having multiple oscillators, adaptively tunes parameters of system components within a signal chain. In this way the system components are tuned to operate within a band tailored to the signal and to the oscillator core. In addition, RF impedances can be matched and power added efficiency can be enhanced in an area efficient monolithic integrated circuit.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: October 11, 2016
    Assignee: Analog Devices Global
    Inventor: James Breslin
  • DC LINEAR VOLTAGE REGULATOR COMPRISING A SWITCHABLE CIRCUIT FOR LEAKAGE CURRENT SUPPRESSION
    Publication number: 20160291618
    Abstract: The present invention relates in one aspect to a DC linear voltage regulator circuit for generating a regulated DC output voltage based on a DC input voltage. The DC linear voltage regulator circuit comprises a DMOS pass transistor comprising drain, gate, source and bulk terminals wherein the drain terminal is connected to a regulator output which is configured to supply the regulated DC output voltage and the source terminal is connected to a regulator input for receipt of the DC input voltage. The DC linear voltage regulator circuit comprises a switchable leakage prevention circuit, connected to the bulk terminal of the DMOS pass transistor, and configured to automatically detect and interrupt a flow of leakage current from the regulator output to the bulk terminal.
    Type: Application
    Filed: March 30, 2015
    Publication date: October 6, 2016
    Applicant: ANALOG DEVICES GLOBAL
    Inventors: Ulrik Sørensen Wismar, Khiem Quang Nguyen
  • Object detection
    Patent number: 9460354
    Abstract: Objects are detected in real-time at full VGA 30 frame per second resolution. A preprocessor performs run-length encoding (RLE) and generates a summed area table (SAT) of an image. The RLE and SAT are used to identify candidate objects and to iteratively refine their boundaries. A histogram of gradients (HoG) and support vector machine (SVM) then reliably classify the object. The method may be part of an advanced driver assistance system (ADAS).
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: October 4, 2016
    Assignee: Analog Devices Global
    Inventors: Joseph Fernandez, Sreenath Kottekkode
  • Cache way prediction
    Patent number: 9460016
    Abstract: In an example, a system and method are provided for predicting in which way a requested memory address is most likely to be held in a multi-way cache, based on the last way accessed by the specified address register if available. If not available, then the system may determine that no best prediction is available. In that case, each way is read, and the superfluous values are disregarded, or a cache fill is performed as necessary. In certain embodiments, only a portion of the least significant bits of an add operation are used for way prediction in base-plus-offset addressing modes. This enables the decision to be made before the full-width add is complete, so that the clock cycle length is not unnecessarily lengthened by the prediction operation.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: October 4, 2016
    Assignee: ANALOG DEVICES GLOBAL HAMILTON
    Inventors: John L. Redford, Michael G. Perkins
  • Digital-to-analog converter with digital charge sharing components
    Patent number: 9455731
    Abstract: A method and a digital-to-analog converter (DAC) circuit involve forming an analog signal using charge sharing operations. The DAC circuit includes a plurality of digital components with associated parasitic capacitances. The digital components are activated based on a digital input code, such that charge is shared among the parasitic capacitances to form a first analog signal proportional to the digital input code. The digital components can also be activated based on a complementary code to form a second analog signal. The first analog signal and the second analog signal can be used to form, as a final output of the DAC circuit, an analog signal that is linearly proportional to the digital input code.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: September 27, 2016
    Assignee: Analog Devices Global
    Inventors: Avinash Gutta, Michael Coln
  • Low drift voltage reference
    Patent number: 9448579
    Abstract: Circuits and method for providing voltage reference circuits that include low drift over time and lower operating voltages are provided. Generally, it is desirable that a reference circuit provide an accurate and precise reference over time. The voltage reference circuits described can provide for good long term stability, operation at lower voltages than prior designs, consistent output voltage with reduced variability due to process changes and mismatches, low noise in the reference voltage, and other advantages.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: September 20, 2016
    Assignee: Analog Devices Global
    Inventor: Stefan Marinca
  • Anti-ringing technique for switching power stage
    Patent number: 9444444
    Abstract: A driver may provide a transition of a switch between an on state and an off state in two stages. In the first stage, the voltage slew rate of the voltage at an output terminal of the switch may be controlled. In the second stage, the current gradient of the switch may be controlled. The transition between the first stage and the second stage may be made based on the value of the voltage at the output terminal of the switch.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: September 13, 2016
    Assignee: Analog Devices Global
    Inventor: Takashi Fujita
  • Multiple stage digital to analog converter
    Patent number: 9444487
    Abstract: In an example, there is disclosed a multi-stage Digital to Analog Convertor, including: a first stage having a first set of circuit components, a second stage having a second set of circuit components and a third stage having a third set of circuit components, the third stage providing a load within first and second individual switchable impedance paths; wherein the DAC is operable in each of a first mode, a second mode and a third mode of operation, wherein in a first mode the first stage is switchably coupled to the second stage independently of the third stage; in a second mode, the load is coupled and presented to a first part of the second stage of circuit components and in a third mode the load is coupled and presented to a second, different, part of the second stage of circuit components. A corresponding system and method is also disclosed.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: September 13, 2016
    Assignee: ANALOG DEVICES GLOBAL
    Inventor: Dennis A. Dempsey
  • Reverse current control for an isolated power supply having synchronous rectifiers
    Patent number: 9438127
    Abstract: In certain example embodiments, a system is provided that includes a circuit. The system also includes a reverse current control module that provides an isolated power supply in order to protect one or more devices in a power chain during one or more testing activities having one or more requirements.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: September 6, 2016
    Assignee: Analog Devices Global
    Inventors: Yingyang Ou, Qingyi Huang, Renjian Xie, Ling Ren
  • Charge pump stage and a charge pump
    Patent number: 9431901
    Abstract: A charge pump cell, comprising: an input node; an output node; Q channels, where Q is an integer greater than one, and where at least two of the channels comprise: a capacitor; a unidirectional current flow device; an output diode; and a channel drive signal node; and wherein a first current flow node of the unidirectional current flow device is connected to a first node of the capacitor at a channel node, a second node of the capacitor is connected to the channel drive signal node, a second current flow node of the unidirectional current flow device is connected to the input node, and the output diode is connected between the channel node and the output node.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: August 30, 2016
    Assignee: Analog Devices Global
    Inventor: Barry P. Kinsella
  • Continuous-time oversampling pipeline analog-to-digital converter
    Patent number: 9432045
    Abstract: A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: August 30, 2016
    Assignee: ANALOG DEVICES GLOBAL
    Inventor: Hajime Shibata
  • Sample rate converter, an analog to digital converter including a sample rate converter and a method of converting a data stream from one data rate to another data rate
    Patent number: 9432043
    Abstract: It is known to perform sample rate conversion. A sample rate converter is arranged to receive digital data at an input sample rate Fs and to output data at an output sample rate Fo, where Fo=Fs/N, and N is decimation factor greater than 1. A problem can arise with sample rate converters when a user wishes to change the decimation rate. Generally a sample rate converter needs to discard the samples in its filter when the decimation rate is changed, and the filter output is unusable until the filter has refilled with values taken at the new decimation rate. The sample rate converter provided here does not suffer from this problem. The sample rate converter includes at least Q channels.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: August 30, 2016
    Assignee: Analog Devices Global
    Inventors: Anthony Evan O'Shaughnessy, Colin Lyden, Joseph Peter Canning
  • Generating comparator thresholds using a rotating ring of resistors
    Patent number: 9425816
    Abstract: Data converters convert signals in analog form to digital form or from digital form to analog form. Due to mismatches between devices that are intended to be identical (unary elements), some data converters outputs may have undesirable characteristics, such as non-linearities. Shuffling the inputs to the unary elements based on a pseudo-random sequence is a technique that can average out the mismatches over time. However, shuffling generally requires a complex switch matrix, and can potentially impact the speed of the converter. To address mismatches, a high speed technique for rotating comparator thresholds is implemented to effectively rotate an array of unary digital-to-analog converter elements. The technique is particularly advantageous for addressing mismatches in unary digital-to-analog converters used for reconstructing a quantized analog signal within delta-sigma analog-to-digital converter.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: August 23, 2016
    Assignee: Analog Devices Global
    Inventors: Wenhua W. Yang, Richard E. Schreier
  • Power-efficient chopping scheme for offset error correction in MEMS gyroscopes
    Patent number: 9419597
    Abstract: Embodiments of the present invention eliminate the high bandwidth buffer from the analog chopper circuit. In some specific embodiments, the buffer is replace with a comparator-based loop that can be used to apply offset correction and achieve N-bit settling performance with sharp (up to 1 ns) rise and fall time with significantly lower power than with a buffer. Other specific embodiments include overcharging circuitry in combination with the comparator-based loop or in lieu of the comparator-based loop. Still other specific embodiments include an array of capacitors in place of the single large capacitor Clarge and use decoding/switching circuitry to selectively couple one of the capacitors into the circuit based on the DAC input code. Importantly, exemplary embodiments result in total power dissipation around the theoretical limit needed to charge the capacitor to the DAC output voltage.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: August 16, 2016
    Assignee: Analog Devices Global
    Inventors: Achal Venkatesh, Abhinav Kumar Dikshit
  • Current measurement
    Patent number: 9411003
    Abstract: The present invention relates to current measurement apparatus. The current measurement apparatus comprises first and second measurement devices with each of the first and second measurement devices being operative to measure current in a respective one of a live conductor and a neutral conductor substantially simultaneously. The current measurement apparatus is operative to make plural different determinations in dependence on the substantially simultaneous current measurements.
    Type: Grant
    Filed: November 22, 2012
    Date of Patent: August 9, 2016
    Assignee: Analog Devices Global
    Inventors: Seyed Amir Ali Danesh, Jonathan Ephraim David Hurwitz
  • Apparatus and methods for a cascode amplifier topology for millimeter-wave power application
    Patent number: 9413309
    Abstract: Provided herein are apparatus and methods for a cascode amplifier topology for millimeter-wave power application. The cascode amplifier can use a neutralized common source stage cascoded with a bootstrapped common gate stage to provide an amplifier topology having enhanced performance, gain, stability and reliability. Additionally, a bootstrap capacitor of the common gate stage can be patterned between the source fingers and the drain fingers of a cascode transistor so as to improve device performance. Operating as an RF power amplifier, a single-stage cascode amplifier using the neutralized common source stage with the bootstrapped common gate stage can provide greater than 15 dB of power gain to signals of the E band.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: August 9, 2016
    Assignee: ANALOG DEVICES GLOBAL
    Inventors: Dixian Zhao, Patrick Reynaert, Michael F. Keaveney