Abstract: An image processor that calculates values that are related to distortion between two image parts. The values are detected in a previous calculation. Those values are then used in the next calculation cycle to detect an early exit. That value, called least, divided by the number of accumulators, and its negative is loaded into the accumulators. When the accumulators reach zero, an early exit is established.

Abstract: A programmable fuse state determination system and method provide a fuse current through a programmed fuse which produces a voltage that varies with the fuse's resistance. The voltage is compared with a threshold voltage to indicate whether the fuse is blown or intact. The invention employs ‘normal’ and ‘test’ modes, in which the relationship between the fuse's resistance and the threshold voltage differ, such that a higher fuse resistance is required for the fuse to be determined blown in the ‘test’ mode than in the ‘normal’ mode.

Abstract: Synthesizers are provided to generate synthesizer signals in response to primary digital signal representations that are created by a signal generator. In an important feature, the synthesizers further include a signal corrector that inserts correction digital signal representations to at least partially cancel a corresponding spurious component in the primary digital signal representation and thereby provide synthesizer signals with reduced spurious content.

Abstract: Methods and structures are provided that reduce conversion errors in pipelined analog-to-digital converters which are induced in one converter cycle by component memory of signals in one or more preceding converter cycles. The methods and structures include the use of digital filters that provide a digital representation of the residue of a preceding converter cycle, multiply this representation by an appropriate memory parameter, and sum the product with the digital representation of the residue of a current converter cycle to thereby reduce the memory effect. The methods and structures also form capacitors of switched-capacitor converter structures with sub-capacitors that are reconfigured (e.g., reversed or alternated between differential sides of differential amplifiers) in different converter cycles.

Abstract: A programmable processor that includes a pipeline with a number of stages. A stall controller is associated with the pipeline, and detects a hazard condition in at least one of those stages. The stall controller produces a set of signals that can control the stages individually, to stall stages of the pipeline in order to avoid a hazard. In an embodiment, a bubble is formed in the pipeline which allows one instruction to complete prior to allowing the pipeline to continue.

Abstract: A new partial product bit generator is used to generate a partial product bit PPji. In some embodiments, the partial product bit generator generates the partial product bit PPji from intermediate signals that are able to be generated concurrently, for example in two levels of combinatorial logic. The partial product bit PPji is then able to be generated from the intermediate signal, for example in only one level of combinatorial logic. In such embodiments, a long series of combinatorial logic operations is not required.

Abstract: A digital latch includes a latch circuit having first and second data inputs, first and second data outputs, and a clock signal input. The latch circuit has a first load value relative to a clock driver when data at the first and second data inputs is non-changing. The latch circuit has a second load value relative to a clock driver when data at the first and second data inputs is changing. The digital latch further includes a load compensation circuit operatively connected to the first and second data inputs of the latch circuit and to the first and second data outputs of the latch circuit.

Abstract: A beam steering module comprised of a mirror stack array in close proximity to a collimator array controllably steers photons along two axis and in a direction substantially less than 90 degrees to the collimator orientation. Several configurations of the module are described using single and double axis mirror rotation and relay optics. Optical telecommunications switches are shown using modules coupled to each other along flat and curved surfaces, with and without use of fold mirror and enabling a plurality of configuration options including photodetector optical power monitoring schemes that require no external power taps.

Abstract: Cascode bias structures are provided which enhance control of cascode biases over disturbing effects such as temperature and process variations. Because this enhanced control stabilizes the biases over these disturbing effects, the biases can be reduced to thereby expand the cascode's dynamic range and yet assure that the cascode transistors continue to operate in their proper transistor regions.

Abstract: A wafer cap protects micro electromechanical system (“MEMS”) structures during a dicing of a MEMS wafer to produce individual MEMS dies. A MEMS wafer is prepared having a plurality of MEMS structure sites thereon. Upon the MEMS wafer, the wafer cap is mounted to produce a laminated MEMS wafer. The wafer cap is recessed in areas corresponding to locations of the MEMS structure sites on the MEMS wafer. The capped MEMS wafer can be diced into a plurality of MEMS dies without causing damage to or contaminating the MEMS die.

Abstract: A switched-capacitor circuit for use in analog-to-digital conversion samples an input signal with respect to a reference voltage such that it significantly reduces a DAC settling time interval during each bit trial. In one exemplary embodiment, the switched-capacitor circuit having first and second groups of capacitor banks is coupled to a first input of a comparator and to a control circuit which provides control signals such that during a switching sequence, an equal value of capacitance is selected from each of the first and second groups of capacitor banks to reduce the DAC settling time interval, thereby improving the conversion rate.

Abstract: An inertial sensor has an interior filled with a relatively low viscosity fill gas. To that end, the inertial sensor has a housing forming the noted interior, and a movable component within the interior. The inertial sensor also has the noted fill gas within the interior. The fill gas has a viscosity that is less than the viscosity of nitrogen under like conditions. For example, when subjected to the same temperatures and pressures, the fill gas has a viscosity that is less than the viscosity of nitrogen.

Abstract: A DAC architecture is described. The architecture is specifically adapted to provided an analog voltage output based on a digital input word. The architecture includes a resistor ladder configuration sub-divisible into a first component, adapted to convert a lower part of the input word, and a second component adapted to convert an upper part of the input word. The DAC is calibrated such that the first component can be used to tune the output of the second component on selection of specific segment from the second component.

Abstract: A JFET switch select circuit including a first current mirror system including a first high current mirror circuit referenced to high rail voltage and a first low current mirror circuit referenced to a low rail voltage, a second current mirror system including a second high current mirror circuit referenced to the high rail voltage and a second low current mirror circuit referenced to the low rail voltage, and a comparator circuit responsive to an input voltage and a reference voltage for directing current from a current supply circuit to one of the first and second high current mirror circuits and one of the first and second low current mirror circuits for saturating a switching device of one of the first and second high current mirror circuits to set a first output voltage proximate to a high rail voltage and for saturating a switching device of one of the first and second low current mirror circuits to set a second output voltage proximate a low rail voltage.

Abstract: A sub-ranging DAC converter is provided where voltage followers rather than operational amplifiers are used to avoid loading a main resistor string.

Abstract: A bandgap voltage reference is described which has reduced sensitivity to noise and amplifier offset. By configuring the circuitry such that the base width of the component transistors is not varied on application of a bias, it is possible to obviate the Early effect.

Abstract: A gain compensation technique for a fractional-N phase lock loop includes locking a reference signal with the N divider feedback signal in a phase lock loop including a phase detector, charge pump, loop filter and voltage control oscillator with an N divider in its feedback loop; driving the N divider with a sigma delta modulator including at least one integrator to obtain a predetermined fractional-N feedback signal; and commanding a scaling in phase lock loop gain by a predetermined factor and synchronously inversely scaling by that factor the contents of at least one of the integrators.

Abstract: Digital filters are provided that include a converter and a data processor. The converter converts successive strings of M successive data elements that occur at a system rate Fs in an input data stream Din to M parallel data elements that respectively occur at a substream rate Fs/M in M data substreams Dsbstrm. At a reduced substream rate Fs/M, the processor generates M convolutions of the filter's quantized impulse response with the M data substreams wherein each of the convolutions is arranged to generate a different one of M successive filtered output signals. Because the convolutions are conducted at the reduced substream rate Fs/M, the filters can operate at increased system rates. Preferably, the digital filter also includes a multiplexer that selects, at the system rate Fs, the M filtered output signals in successive order to thereby form a filtered output data stream Dout.

Abstract: A circuit with a common-mode dual output includes a feedback circuit connected to alternate the states of the dual output between an average output level and a desired common-mode level. The difference between the average and desired levels is proportional to a signal offset level. An impedance matching circuit is connected to the feedback circuit to adjust the signal offset level.

Abstract: A method converts an input data rate associated with N units of data to an output data rate associated with M units of data. The method includes calculating N write-control parameters each associated with one of M addresses of an output memory, directing each of N values of input data to an associated address of the output memory in response to the N calculated write-control parameters, and reading the output memory to provide output data associated with the output data rate. If N is greater than M, some of the N write-control parameters are associated with at least one shared address of the M addresses. If M is greater than N, all of the N write-control parameters are associated with different addresses of the M addresses. An apparatus is configured to implement this method.