Abstract: A system for randomizing aperture delay in a time interleaved ADC system that includes a plurality of selection switch stages corresponding to each of the ADCs in the system and a second selection switch stage coupled to a voltage source. A plurality of conductors extend between the second selection switch stage and each of the selection switch stages, in excess of the number of ADCs in the system. For each of N ADCs in the system, the selection switch stages and the second selection switch stage support at least N+1 selectable conductive paths extending from each of the sampling capacitors of the ADCs to the voltage source. Random selection of the N+1 paths can randomize aperture delay.

Abstract: Filter system embodiments are provided for realizing interpolation and decimation processes with interleaved filter structures. These interleaved structures enable the systems to obtain output data rates that exceed the highest operation rates of the system components.

Abstract: A device and method for correlation-based background calibration of pipelined converters with a reduced power penalty. A pipelined analog-to-digital converter (ADC) utilizes a random or pseudorandom signal to reduce the quantization error of subconverting stages. Stages within the ADC comprise an injection circuit having a plurality of capacitive branches in parallel. Less than all of the branches can function during a given clock cycle of the ADC. This allows a subconverting stage within the ADC to be accurately trimmed before operation using a large amplitude signal. At the same time, the capability to inject smaller amplitude random or pseudorandom signals into the subconverting stage during operation is maintained, saving valuable dynamic range and power. The various capacitive branches are cycled through either randomly or in sequence such that the quantizer manifests the same average gain error over time for which the quantizer was initially trimmed.

Abstract: A vehicle engine sound simulator includes a crossfade sample playback engine which produces an output waveform comprising at least two constituent waveforms which are transposed up and down in frequency with RPM. The playback engine's output waveform is provided to at least one digital signal processing (DSP) circuit, which processes the output with a function that varies with the rate of change of RPM, an external load value, and/or a combination of both to produce the simulator's output. The crossfade sample playback engine is arranged to crossfade between at least 2 wave samples as RPM changes. Wave samples from additional wave banks associated with different load states can also be mixed into the playback engine's output waveform. The DSP circuit can include both nonlinear and linear processing sections in various combinations.

Abstract: A low voltage shutdown circuit comprises an input node for receiving a voltage Vin to be monitored, first and second voltage-to-current (V to I) converters arranged to receive Vin at respective inputs and to convert Vin to currents I1 and I2 at respective outputs, and a current comparison circuit arranged to produce an output which is in a first state when I1<I2 and in a second state when I1>I2. The V to I converters have respective voltage-to-current transfer functions which intersect at a non-zero threshold voltage Vth, such that the current comparison circuit output toggles when Vin<Vth. This output can be used as needed to, for example, trigger the shut down of other circuitry.

Abstract: An input stage receives a differential input signal at first and second input nodes and provides a differential output current at first and second output nodes. The differential output current includes a component taken from the input nodes through first and second impedances, and an additional component generated in response to a sample of the voltage of the differential input signal. A transconductance cell having cross-coupled inputs may generate the additional component of the output current.

Abstract: A system for verifying the identification of a device. A codec is configured to measure at least one electrical characteristic of a device connected to a jack and to identify the device based on the measured electrical characteristic. An updateable database is populated with the electrical characteristic of at least one device whose electrical characteristic was measured by the codec but not correctly identified by the codec and a software routine is responsive to the measured electrical characteristic and configured to adjust the codec's identification of the device based on the electrical characteristic stored in the database to correctly identify the device.

Abstract: The method and system for converting an analog value into a digital equivalent using a plurality of conversion engines are disclosed. In one embodiment the plurality of conversion engines comprise N DACs associated with M comparators, wherein M is substantially greater than N, wherein M and N are integers, wherein each of the N CAP DACs has an associated P CAP DAC and an N CAP DAC, a method includes generating voltage differences between P CAP DACs and N CAP DACs such that they produce M threshold voltages. The plurality of conversion engines operate in a first phase of the conversion by inputting the produced M threshold voltages to associated inputs of M comparators so that more than one bit can be determined from a sampled signal during each successive approximation trial.

Abstract: A system for converting digital signals into analog signals using sigma-delta modulation and includes a signed thermometer encoder for converting a plurality of signed binary data received at the encoder into a plurality of signed thermometer data and a rotational dynamic element matching (DEM) arrangement for receiving the plurality of signed binary data and the plurality of signed thermometer data. The rotational DEM arrangement further includes a first barrel shifter for receiving a positive thermometer data at a cycle, the first barrel shifter having a first pointer indicating a starting position of next positive thermometer data, and a second barrel shifter for receiving a negative thermometer data at a cycle, the second shifter having a second pointer indicating a starting position of next negative thermometer data, wherein the first pointer is circularly shifted as a function of positive binary data and the second pointer is circularly shifted as a function of negative binary data.

Abstract: Electronics packages are provided with structure that provides a significantly-reduced package footprint and also facilitates substantial reduction of package fabrication time and cost. The footprint reduction is realized with a frame that defines an aperture wall which surrounds first sets of components on the first side of a printed circuit board and also extends away from the printed circuit board to provide package input/output access along the perimeter of the package footprint. The second side of the printed circuit board receives a second set of components and this set is protected by a board fill. The frame and printed circuit board are configured for realization from frame and board panels whose planar forms substantially reduce package fabrication time and cost because they facilitate the use of modern high-speed printed circuit board (PCB) fabrication processes.

Abstract: A phase detector includes a first clock driver comprising a first LC tank. The first clock driver provides a strobe to a plurality of flip-flops associated with sampled data being received by the phase detector. The second clock driver includes a second LC tank. The second clock driver provides a strobe to a plurality of flip-flops associated with sampling the phase error of the phase detector. The first and second LC tanks have different adjustable center frequencies and experience a programmable delay between the outputs of the first and second clock drivers so as to determine the data sampling phase of the phase detector.

Abstract: A semiconductor device interconnection contact and fabrication method comprises fabricating one or more active devices on a semiconductor substrate. A diffusion barrier layer is deposited over the devices, followed by an Al-based metallization layer. The diffusion barrier and metallization layers are masked and etched to define interconnection traces. Mask and etch steps are then performed to remove interconnection trace metallization that is in close proximity to the active device regions, while leaving the traces' diffusion barrier layer intact to provide conductive paths to the devices, thereby reducing metallization-induced mechanical stress which might otherwise cause device instability.

Abstract: An RF measurement system includes an envelope detector to extract the modulation envelope of the RF input signal. The resulting baseband envelope signal is then applied to a statistics extraction circuit which provides a precise measure of the modulation envelope. The statistics extraction circuit can be implemented with any number of lower-frequency precision measurement technologies because the high-frequency carrier portion of the signal is removed, and thus, the demands on the post-envelope extraction circuit are greatly reduced. In one embodiment, the envelope detector and statistics extraction circuit may be implemented as a logarithmic amplifier followed by an RMS-responding post-processing circuit to provide accurate power measurement.

Abstract: Embodiments of the present invention provide a drive signal for a motor-driven mechanical system whose frequency distribution has zero (or near zero) energy at the expected resonant frequency of the mechanical system. The drive signal may be provided as a pair of steps sufficient to activate movement of the mechanical system and then park the mechanical system at a destination position. The steps are spaced in time so as to have substantially zero energy at an expected resonant frequency fR of the mechanical system. The drive signal may be filtered to broaden a zero-energy notch at the expected resonant frequency fR.

Abstract: A drive signal for a motor-driven mechanical system has zero (or near zero) energy at an expected resonant frequency of the mechanical system. The drive signal may be provided in a series of steps according to a selected row of Pascal's triangle, wherein the number of steps equals the number of entries from the selected row of Pascal's triangle, each step has a step size corresponding to a respective entry of the selected row of Pascal's triangle, and the steps are spaced from each other according to a time constant determined by an expected resonant frequency of the mechanical system.

Abstract: Digital potentiometer architecture is disclosed, composing of an integrated circuit containing multiple string arrays, each having a plurality of switching devices and an array of resistors. The insertion of an additional string array between the input terminals and the wiper, allows for the disconnection of a common string array and for the independent calibration of the resistance between each input terminal and the wiper.

Abstract: A drive signal for a motor-driven mechanical system has zero (or near zero) energy at an expected resonant frequency of the mechanical system. The drive signal may be provided in a series of steps according to a selected row of Pascal's triangle, wherein the number of steps equals the number of entries from the selected row of Pascal's triangle, each step has a step size corresponding to a respective entry of the selected row of Pascal's triangle, and the steps are spaced from each other according to a time constant determined by an expected resonant frequency of the mechanical system.

Abstract: An H-bridge controller and a method for controlling a common-mode voltage and/or current of an H-bridge circuit are disclosed. In one embodiment, an H-bridge controller includes a section for receiving a signal indicating at least one of a common-mode voltage or common-mode current of the H-bridge circuit, and a section for generating control signals which determine switching of the H-bridge circuit so as to control at least one of the common-mode voltage or common-mode current of the H-bridge circuit. In another embodiment, a method for controlling a common-mode voltage and/or current of an H-bridge circuit includes receiving a signal indicating at least one of a common-mode voltage or common-mode current of the H-bridge circuit; and generating control signals which determine switching of the H-bridge circuit so as to control at least one of the common-mode voltage or common-mode current of the H-bridge circuit.

Abstract: An analog to digital converter is provided in which the outputs of first and second digital to analog converters DAC1 and DAC2 are combined in a combining circuit so as to form a plurality of decision thresholds. This enables two or more bits to be determined in a single trial.

Abstract: A digital current share bus interface connects to a power module which provides a signal representative of its output current, and adjusts the module's output current in response to a control signal received from the interface. A data formatting module receives the output current signal and generates a digital word that varies with the current; the bits of the word are coupled to a current share bus. A comparator module receives digital words conveyed via the bus and generated by the data formatting module at respective inputs, and provides the control signal to the power module so as to adjust its output current to match the current value represented by the digital word on the bus. In a typical implementation, multiple power modules are coupled to the current share bus via respective interfaces, with the output currents of all the power modules connected in parallel.