Abstract: A method and apparatus for extending the linear range of a phase detector. In one embodiment, a limited range phase difference is generated between selected edges of first and second input signals, and an excursion of the limited range phase difference beyond a predetermined threshold is detected. In response to detecting the excursion of the limited range phase difference beyond a threshold, an edge of the first or second input signal is prevented from influencing subsequent generation of the limited range phase difference, and a compensated phase difference is generated, derived from the limited range phase difference and including a correction component which compensates for the effect of preventing said edge from influencing subsequent generation of the limited range phase difference.

Abstract: Methods and apparatus for handling speculative addresses in a pipelined digital processor are provided. A digital signal processor includes an address generator configured to generate speculative data addresses, a pipelined execution unit configured to execute instructions using data at locations specified by the speculative data addresses, a speculative register file configured to hold the speculative data addresses as corresponding instructions advance through the execution unit, an architectural register file configured to hold architectural data addresses, and control logic configured to write speculative data addresses to the speculative register file as the speculative data addresses are generated by the address generator and to supply speculative data addresses or architectural data addresses to the address generator. The speculative register file may be configured with sufficient capacity to hold one or more architectural data addresses.

Abstract: Methods and apparatus are provided for achieving low latency for high priority tasks in digital processing systems. A digital signal processor includes a core processor and a level one memory. In some embodiments, a store buffer is configured to hold write information for the level one memory and for a level two memory. A write buffer is configured to hold write information, received from the store buffer, for the level two memory. The write buffer has a normal capacity and an excess capacity. A memory controller enables the excess capacity of the write buffer when a high priority task is being serviced and inhibits write access to the excess capacity of the write buffer when a high priority task is not being serviced. In other embodiments, the digital signal processor includes first and second fill buffers configured to hold read data in a fill operation. The memory controller steers low priority read data to the first fill buffer or the second fill buffer based on priority of the fill operation.

Abstract: A DMA controller includes at least one peripheral DMA channel for handling DMA transfers on a peripheral access bus; at least one memory DMA stream, including a memory destination channel and a memory source channel, for handling DMA transfers on first and second memory access buses; first and second address computation units for computing updated memory addresses for DMA transfers; and first and second memory pipelines for supplying memory addresses to the first and second memory access buses, respectively, and for transferring data on the first and second memory access buses. Channel control logic controls transfer of data through the DMA channels in response to parameters contained in at least one DMA descriptor having a programmable format.

Abstract: Methods and apparatus are provided for processing variable width instructions in a pipelined processor. The apparatus includes an instruction decoder configured to decode a loop setup instruction, having a loop setup instruction address, to obtain a loop bottom offset and configured to decode instructions following the loop setup instruction, each having an instruction address, to obtain an instruction width, registers for holding the loop setup instruction address and the loop bottom offset, and a loop bottom detector, responsive to a current instruction address, a current instruction width, the loop setup instruction address and the loop bottom offset, configured to determine if a next instruction is a loop bottom instruction.

Abstract: A DMA controller includes at least one peripheral DMA channel for handling DMA transfers on a peripheral access bus; at least one memory DMA stream, including a memory destination channel and a memory source channel, for handling DMA transfers on first and second memory access buses; first and second address computation units for computing updated memory addresses for DMA transfers; first and second memory pipelines for supplying memory addresses to the first and second memory access buses, respectively, and for transferring data on the first and second memory access buses; and a multiplexer configured to supply first and second current memory addresses to selected ones of the first and second memory pipelines in response to a control signal.

Abstract: A circuit and method are provided enabling the transfer of signals from a first voltage domain to a second voltage domain. The circuit comprises level shifters enabling the signal transfer, and is space-efficient and power efficient. A 3-wire serial protocol is used to enable the serial transmission of signals across the voltage domain boundary, and provides two distinct reset states.

Abstract: A circuit and method are provided to enable the synchronization of an on-demand, synchronous signal with an asynchronous signal. The synchronous signal is activate only for a portion of the period of the asynchronous signal, thus providing beneficial power conservation. The synchronous signal is activated in response to a first edge of the asynchronous signal, and deactivated in response to a second edge of the asynchronous signal.

Abstract: An intermediate electrode layer is used to fabricate an integrated micro-electromechanical system. An intermediate electrode layer is formed on an integrated circuit wafer. The intermediate electrode layer places drive electrodes a predetermined height above the surface of the integrated circuit wafer. A micro-electromechanical system wafer having micromachined optical mirrors is bonded to the integrated circuit wafer such that the drive electrodes are positioned a predetermined distance from the optical mirrors.

Abstract: Methods and apparatus for varying and measuring the position of a micromachined electrostatic actuator using a pulse width modulated (PWM) pulse train are disclosed. One or more voltage pulses are applied to the actuator. In each of the pulses, a voltage changes from a first state to a second state and remains in the second state for a time tpulse before returning to the first state. The position of the actuator may be varied by varying the time ?tpulse. A position of the actuator may be determined by measuring a capacitance of the actuator when the voltage changes state, whether the time t is varied or not. An apparatus for varying the position of a MEMS device may include a pulse width modulation generator coupled to the MEMS device an integrator coupled to the MEMS device and an analog-to-digital converter coupled to the integrator. The integrator may measure a charge transferred during a transition of a pulse from the pulse generator.

Abstract: A hybrid matching system is disclosed for use with a transmitter and receiver. The hybrid matching system includes a pair of transmitter output nodes, a pair of receiver input nodes, and a pair of terminals for interfacing to a transmission line. The system further includes a first impedance bridge portion including at least one inductor for coupling to the transmission line terminals via at least one transformer winding, and a second impedance bridge portion interposed between the pair of transmitter output nodes and the first impedance bridge portion, and interposed between the pair of receiver input nodes and the first impedance bridge portion.

Abstract: A fiber-attached optical device with in-plane micromachined mirrors includes a cover having at least one reflector formed on one side and a substrate having a plurality of micromachined optical mirrors formed substantially on a single plane on a side facing toward the mirrored side of the cover. The micromachined optical mirrors are controllable to reflect optical signals between a plurality of optical fiber segments via the at least one reflector. The plurality of optical fiber segments can be attached to either the cover or the substrate so as to form an integrated package including the substrate, the cover, and the plurality of optical fiber segments. The mirrors can be controlled to variably attenuate the optical signals.

Abstract: A variable modulus interpolator (1) for interpolating a fractional part F M of a rational number by which a reference frequency is to be divided in a multi-divisor divider in a variable frequency synthesizer comprises a third order sigma-delta modulator (3) of MASH cascade configuration having first, second and third sigma-delta stages (5,6,7). The numerator F of the fraction is selectable and is inputted to a first register (10) for inputting to the input of the first sigma-delta stage (5) of the sigma-delta modulator (3). The denominator M of the fraction is selectable and is inputted to a second register 11. A single bit output quantiser (16) in each sigma-delta stage (5,6,7) outputs a sign bit indicative of the sign of the output from an integrator (15) in the corresponding sigma-delta stage (5,6,7).

Abstract: Methods of making microelectromechanical combdrive devices are disclosed. The device may optionally be formed using three device layers. A moveable element and flexure may be formed from a first device layer. The second device layer may be attached to the first and a first set of comb teeth are formed from the second device layer. One or more comb teeth in the first set extend from a major surface of the moveable element. A third device layer is attached to the second device layer and a second set of comb teeth are formed from the third device layer. An alignment target is formed in the first device layer. Corresponding alignment holes are formed in the second or third device layers.

Abstract: A micromachined device has a body suspended over a substrate and movable in a plane relative to the substrate. The body has a perimeter portion, a first cross-piece portion extending from one part of the perimeter portion to another part of the perimeter portion to define at least first and second apertures, a first plurality of fingers extending along parallel axes from the perimeter portion into the first aperture, and a second plurality of fingers extending along parallel axes from the perimeter portion into the second aperture.

Abstract: A sigma delta modulator includes a modulator module that includes a quantizer with variable hysteresis, which receives an input signal to perform necessary modulation operations. A non-linear mapping module receives a signal associated with said input signal and tabulates the necessary hysteresis control information so as to reduce the transition rate of the modulator module.

Abstract: A receiver circuit is disclosed for use in a communication system. The receiver circuit includes a forward path with a channel selection filter and a feedback path. The output of the channel selection filter is provided to an output device. The feedback path includes a feedback filter and a mixer. The input of the feedback filter is coupled to the output of the channel selection filter and the output of the feedback filter is coupled to a first input of the mixer. The second input of the mixer is coupled to a multi-frequency signal generator, and the output of the mixer is coupled to the forward path of the receiver circuit.

Abstract: A transceiver system is disclosed for use in a telecommunication system. The transceiver system includes a transmission circuit including a transmitter input coupled to an input of a transmission amplifier, a receiver circuit including a receiver output coupled to an output of a receiver amplifier, and a transmission line interface circuit that is coupled to an output of the transmission amplifier and to an input of the receiver amplifier. The transmission line interface circuit includes a matching impedance that is directly coupled to a feedback path of the transmission amplifier and that terminates the transmission line of the transceiver system.

Abstract: A multi-channel circuit (1) comprising a plurality of on-chip channels (CH1 to CH4), each of which comprises a DAC (3) for converting digital data into analogue output signals independently of each other under the control of an interface and control logic circuit (11). The analogue output signals from the DACs (3) are outputted on output terminals (7) of the respective channels (CH1 to CH4). The digital input data and control and address signals for controlling the conversion of the digital data in the DACs (3) are inputted to the interface and control logic circuit (11) through an I/O port (10). DAC registers (9) are provided in the respective channels (CH1 to CH4) for storing the digital words to be converted in the corresponding DACs (3). Analogue input terminals (20) are provided for receiving analogue input signals (20), for example, analogue signals from external systems which may be controlled by the output signals from the DACs (3).

Abstract: A multi-channel analog to digital converter which facilitates calibration of the analog to digital converter and respective input channels to the analog to digital converter, and a method for calibrating the analog to digital converter. A multi-channel ADC (1) comprising an ADC circuit (2) for converting analog signals received on input channels CH1 to CHN to digital output signals comprises a primary offset storing register (24) and a primary gain storing register (25) for storing respective primary offset and gain correction codes which are applied to the digital output signals in a primary correcting circuit (14) for correcting for the offset and gain errors introduced by the ADC circuit (2).