Abstract: An analog to digital converter is provided which has a compact serial interface utilising only four pins to define chained and non chained modes of operation. Further more the interface also allows the converter to be configured to indicate immediately that the conversion has been completed. Another variant of the invention enables an analog to digital converter to be provided having only a 3 pin serial interface.

Abstract: An integrated circuit including a DMA controller, an ADC having a plurality of conversion channels and address and data ports for connection to external memory means, the DMA controller being arranged to read a channel id from the memory means using the address and data port which channel id is representative of one of the said conversion channels, to pass the read channel id to the ADC, to cause the ADC to perform an analog-to-digital-conversion on the conversion channel represented by the channel id, to receive the conversion result from the ADC and to write the conversion result back to the memory means using the address and data ports.

Abstract: Data driver systems are provided that have programmable modes of operation to thereby facilitate selection of output signal forms and reduction of output ports in signal conditioning systems (e.g., analog-to-digital converters). The systems effectively reduce pin count by sharing pins between different drivers and selectively configuring the drivers in driver and high output-impedance states.

Abstract: An image processor that calculates values that are related to distortion between two image parts. The values are detected in a previous calculation. Those values are then used in the next calculation cycle to detect an early exit. That value, called least, divided by the number of accumulators, and its negative is loaded into the accumulators. When the accumulators reach zero, an early exit is established.

Abstract: An amplifier utilizes feedback compensation to extend bandwidth. A feedback network is coupled between an output stage and an intermediate stage. One or more resistors in the feedback network can be arranged to compensate for Early voltage effects in one or more transistors in the intermediate stage. One or more capacitors in the feedback network can be arranged to cancel the junction capacitance of one or more transistors in the intermediate stage.

Abstract: A signal processing circuit comprising an ADC (5) to which differential signals and pseudo-differential signals are switched through two multiplexors (8) and (9). Positive input signals are buffered to a positive input terminal (6) of the ADC (5) through a buffer (12). Negative input signals are buffered through a conditioning circuit (15) to a negative input terminal (7) of the ADC (5). The conditioning circuit (15) comprises a buffer circuit (16) having a buffer (18), through which input signals are selectively buffered to the negative input terminal (7) of the ADC (5), and a bypass circuit (17) which bypasses the buffer circuit (18) for selectively passing input signals unbuffered to the negative input terminal (7) of the ADC 5.

Abstract: An operational amplifier provides independent trimming of Vos for both high and low common mode input voltages. The amplifier includes complementary input pairs, and employs a steering circuit which provides a tail current Itail to one pair when Vcm is less than a threshold voltage Vth, and provides Itail to the other pair when Vcm>Vth. The input pairs drive a load stage which includes one or more trim inputs that enable Vos to be varied with one or more trim signals applied to the trim inputs. A first trim signal generating circuit provides a first trim signal only when Vcm<Vth, and a second trim signal generating circuit provides a second trim signal to a trim input only when Vcm>Vth. This allows the input offset voltages at high and low Vcm to be adjusted independently.

Abstract: An apparatus having a core processor and a plurality of cache memory banks is disclosed. The cache memory banks are connected to the core processor in such a way as to provide substantially simultaneous data accesses for said core processor.

Abstract: Simple, inexpensive boost structures are realized with diode, switch and buffer circuits that operate in a charge mode and a boost mode to thereby generate a boost signal Sboost. The boost structures are especially suited for use in switched-capacitor systems.

Abstract: Phase-locked loop methods and structures are provided for generating modulated communication signals with nonconstant envelopes. These methods and structures realize the improved communication performance of nonconstant-envelope modulations with the upconversion advantages of phase-locked loops. The structures include transmitters in which a phase-locked loop is augmented with first and second feedforward paths that substantially restore phase and amplitude information to a transmit signal that is generated by a voltage-controlled oscillator of the phase-locked loop. The first feedforward path is configured to realize a path transfer function of s/Kv wherein the voltage-controlled oscillator has a transfer function of Kv/s. The second feedforward path extracts an envelope-correction signal from the modulated intermediate-frequency signal and a variable-gain output amplifier amplifies the transmit signal with a gain that responds to the envelope-correction signal.

Abstract: A one-time end-user-programmable fuse array circuit suitable for providing a digital input to a programmable analog element such as a DAC. An end-user-specified digital bit pattern is conveyed to a programming circuit, which programs an array of data fuses in accordance with the specified pattern. A validation means indicates whether the states of the data fuses match the specified pattern. The programming circuit blows a “lock” fuse when the data fuses match the specified pattern, which prevents any additional data fuses from being programmed. The specified pattern and the states of the data fuses are multiplexed to a programmable analog element. Initially, the end-user can vary the pattern to achieve a desired result from the programmable element. When the desired result is achieved, the data fuses are blown, the resulting pattern is validated, and the lock fuse is blown—thereby providing a permanent trim signal.

Abstract: A micromachined device has a body suspended over a substrate and movable in a plane relative to the substrate. The body has a perimeter portion, a first cross-piece portion extending from one part of the perimeter portion to another part of the perimeter portion to define at least first and second apertures, a first plurality of fingers extending along parallel axes from the perimeter portion into the first aperture, and a second plurality of fingers extending along parallel axes from the perimeter portion into the second aperture.

Abstract: A power-on reset system insensitive to the ramp up rate of supply voltage VDD includes two power-on reset circuits. The first reset circuit asserts a reset signal RS1 when supply voltage VDD ramps up to its rated voltage. The second reset circuit produces a first reference voltage VR1 and a second reference voltage VR2 which is delayed with respect to VR1, and asserts a reset signal RS2 when VR1 is greater than VR2. A logic gate asserts a reset signal RS3 when either RS1 or RS2 is asserted; RS3 is the output of the power-on reset system, and is asserted whether one or both of reset signals RS1 and RS2 is asserted. Both reset circuits are preferably arranged to operate with supply voltages of 2 volts or less.

Abstract: Pipelined ADC systems are provided with gain-matching structures that substantially eliminate gain errors between preceding and succeeding converter stages. These structures include reference signal-conditioning elements which mimic at least one of main signal-conditioning elements in the succeeding converter stages. The reference signal-conditioning elements control reference signals which maintain a match between the full-scale range of a digital-to-analog converter (DAC) in a succeeding stage and the “gained-up” step size of a DAC in a preceding stage. This match substantially eliminates the gain errors.

Abstract: A probe card characterizes optical structures formed on a MEMS wafer. The probe includes a substrate having a circuit thereon. The substrate has an opening wherein a plurality of metal probes, electrically coupled to the circuit, pass through the opening. The probe card further includes an optical test device electrically coupled to the circuit. The optical test device includes a light source and a photosensitive area. The photosensitive area receives directly light reflected from the optical structures. The optical test device can be positioned directly over the opening, or the optical test device can be positioned on a periphery of the opening. Furthermore, the optical test device can be positioned so as to provide a test light beam that is parallel to the wafer to test pop-up optical MEMS components. The optical test device also may be positioned between the probe card and the MEMS wafer.

Abstract: Static read/write memory structures are provided that include predetermined latent-state patterns which can be retrieved with a latent-state retrieve process that differs somewhat from a conventional write process. The patterns are realized with threshold-voltage differences and they significantly enhance flexibility of memory allocation without increasing memory area nor significantly altering conventional read/write processes.

Abstract: An N-phase switching voltage regulator includes N current sensing elements which carry respective phase currents. The voltages present at the switch node sides of the sensing elements are summed and presented to an amplifier which also receives the regulator's output voltage, to produce an output which is proportional to the regulator's total output current Iout. The invention also provides a means for direct insertion of total inductor output current information into a regulator's voltage-mode control loop, to provide active voltage positioning (AVP) for the output voltage. A voltage based on total inductor output current is summed with the regulator's reference voltage; this sum and Vout are applied to the voltage control error amplifier, the output of which is processed to operate the regulator's switches. This enables the regulator's output to have a desired droop impedance and to provide AVP of Vout as a function of total filtered inductor output current Iout(fltr).

Abstract: A method for placing a device in a reduced power-consumption mode of operation. The method comprises the steps of initializing a device select signal into a first logic state, asserting the device select signal in a second logic state, and returning the device select signal to the first logic state within a first predetermined time window. A device is also described that includes means for detecting logic state transitions at a device select input and a clock input, and means for changing operating mode of the device in response to a predetermined number of logic state transitions at the clock input, occurring between logic state transitions at the device select input.

Abstract: A hiccup-mode short circuit protection circuit and method for a linear voltage regulator using a FET pass transistor uses the capacitance of the pass transistor's gate as a timing element. The regulator's output voltage is monitored, and when it droops below a voltage indicative of a short-circuit condition, the regulator's drive signal is disconnected from the pass transistor. While the short-circuit condition persists, a first current is provided to charge the pass transistor's gate capacitance. When the gate voltage rises above a first predetermined threshold, a second current is provided to further charge the gate capacitance. When the gate voltage rises above a second predetermined threshold, the gate capacitance is discharged. The gate capacitance is cyclically charged and discharged in this way unless the output voltage rises to indicate that the short-circuit condition has cleared, in which case the regulator's drive signal is restored to the pass transistor's gate.

Abstract: Methods and apparatus are provided for transferring data words from a source to a destination. The apparatus includes a datapath buffer coupled by a first data bus to the source and coupled by a second data bus to the destination, write control logic for writing a first number of data words in the datapath buffer in response to a first source transfer condition and for writing a second number of data words in the datapath buffer in response to a second source transfer condition, and read control logic for reading the first number of data words from the datapath buffer in response to a first destination transfer condition and for reading the second number of data words from the datapath buffer in response to a second destination transfer condition.