Abstract: A bandgap voltage reference circuit that can be implemented with low noise characteristics is described. To achieve such low noise, a bandgap reference circuit is provided that includes an amplifier coupled at its inputs to first and second transistors respectively, the transistors being arranged to generate a voltage representative of the base emitter voltage differences between each of the first and second transistors across a sensing resistor. The circuit additionally provides an additional current to the sensing resistor to reduce the noise contribution into the amplifier from the first transistor. Such a circuit may be corrected for second order temperature effects by inclusion of a temperature dependent current source.

Abstract: Disclosed is a method and circuit for dissipating injected parasitic charge including a circuit stage, a pulse generating circuit and a switch. The circuit stage having an input node and an output node that injects a parasitic charge when switched OFF to the output node. The pulse generating circuit can generate a pulsed signal having an input for receiving a control signal. The control signal indicates the circuit stage is switching OFF, and has an output for outputting a pulsed signal in response to the control signal at the input. The pulsed signal can have a predetermined duration. The switch can be configured to be actuated by the pulsed signal output by the pulse generating circuit, and having a terminal connected to the output node of the circuit stage and a terminal connected to circuit to substantially dissipate the injected parasitic charge.

Abstract: An electronics package has a wafer level chip scale package (WLCSP) die substrate containing electronic circuits. Through-silicon vias through the die substrate electrically connect the electronic circuits to the bottom surface of the die substrate. A package sensor is coupled to the die substrate for sensing an environmental parameter. A protective encapsulant layer covers the top surface of the die substrate. A sensor aperture over the package sensor provides access for the package sensor to the environmental parameter.

Abstract: A system and method are provided for isolating an input without adding significant distortion and without significantly adversely affecting the bandwidth of input circuits. In one embodiment, a single ended signal is substantially cancelled by an arrangement including an input resistance path in parallel with a negative resistance path wherein both paths substantially match in resistance. In another embodiment, a differential signal is substantially cancelled by a pseudo differential arrangement including two independent input resistance paths each in parallel with a corresponding negative resistance path, wherein the resistance paths substantially match the input resistance paths.

Abstract: In one aspect, an apparatus for data conversion is provided.

Abstract: A thin film resistor (5) of an integrated circuit comprises an elongate resistive film (7) extending between electrical contact pads (10,11). A low impedance element (20) overlays and is electrically coupled to a portion of the resistive film (7) in an intermediate portion (22) thereof adjacent a second side edge (17) of the resistive film (7) for conducting current in parallel with the intermediate portion (22), and for reducing current density in the intermediate portion (22). First and second transverse edges (28,29) formed by spaced apart first and second slots (26,27) which extend from a first side edge (16) into the resistive film (7) define with a first side edge (16) of the resistive film (7) and the low impedance element (20) first and second trimmable areas (30,31) in the intermediate portion (22).

Abstract: A bandgap voltage reference circuit with an inherent curvature correction which comprises an amplifier having an inverting terminal, a non-inverting terminal and an output terminal is described. A first and second bipolar transistor operable at different current densities are provided each of the transistors being coupled to a corresponding one of the inverting and non-inverting terminals of the amplifier such that a ?Vbe is reflected across a first load element. A current biasing circuit is provided which includes a semiconductor device coupled to each of the first and second bipolar transistors and is configured for applying a non-linear bias current to the first and second bipolar transistors for biasing thereof.

Abstract: A bias current generator for generating bias current is described. The generator comprises an amplifier having an inverting input, a non-inverting input and an output. A first bipolar transistor is associated with one of the inverting and non-inverting inputs of the amplifier. A load MOS device is associated with the other one of the inverting and non-inverting inputs of the amplifier. The load MOS device is driven by the amplifier to operate in the triode region with a corresponding drain-source resistance ron. The first bipolar transistor and the load MOS device are arranged such that a voltage derived from the first bipolar transistor is developed across the drain-source resistance ron of the load MOS device thereby generating a bias current.

Abstract: A reference voltage circuit which is less dependent on semiconductor process variations compared to bandgap based reference voltage circuits. The circuit comprises a first amplifier having an inverting input, a non-inverting input and an output. A current biasing circuit provides first and second PTAT currents, and a CTAT current. The CTAT current is equal in value to the second PTAT at a first predetermined temperature and opposite in polarity. A first load element is coupled to the non-inverting input of the first amplifier and arranged for receiving the first PTAT current such that a PTAT voltage is developed across the first load element. A feedback load element is coupled between the inverting input and the output of the amplifier for receiving the summation of the CTAT current and the second PTAT current.

Abstract: A bandgap voltage reference circuit which provides a bandgap reference voltage without requiring a resistor. The circuit comprises an amplifier having an inverting input, a non-inverting input and an output. First and second bipolar transistors are provided which operate at different current densities each coupled to a corresponding one of the inverting and non-inverting inputs of the amplifier. A load MOS transistor of a first aspect ratio is driven by the amplifier to operate in the triode region with a corresponding drain-source resistance ron. The load MOS device is operably coupled to the second bipolar transistor such that a base-emitter difference (?Vbe) resulting from the collector current density difference between the first and second bipolar transistors is developed across the drain-source resistance ron, of the load MOS device. A cascoded MOS device of a second aspect ratio is operably coupled to the load MOS device and is driven by the amplifier to operate in the triode region.

Abstract: An apparatus and method for inter-channel data exchange in multi-channel data acquisition systems is disclosed. A multi-channel data acquisition system may include a data exchange layer coupling two or more channels of the data acquisition system. Data may be transmitted via the data exchange layer between the channels, enabling data from one channel to be processed and output by another channel. The data exchange layer may include serial or parallel communication means.

Abstract: A method of capturing an event in a MEMS accelerometer stores acceleration data in memory, detects a trigger event based on the acceleration data, and modifies a configuration of the memory so that a specified amount of the acceleration data is saved. A MEMS event capturing system includes an inertial sensor having sensor circuitry and event capturing circuitry implemented with the sensor circuitry. The event capturing circuitry includes memory capable of storing acceleration data received from the inertial sensor and a detection module operatively coupled with the memory that detects a trigger event. The event capturing circuitry also includes a management module operatively coupled with the memory and the detection module that modifies the memory's storage configuration when the trigger event is detected.

Abstract: A system, computer program product and method of obtaining a performance parameter associated with a sensor, such as an accelerometer, is provided. The method includes applying an acceleration to the accelerometer and a first frequency to obtain a sensitivity of the accelerometer at the first frequency. A first self-test is performed on the accelerometer. The first self-test includes stimulating the accelerometer with a first self-test stimulation signal encoded with the first frequency, such that the accelerometer outputs a first signal. A self-test equivalent acceleration is then determined based, at least in part, on the first signal and the accelerometer sensitivity at the first frequency. A second self-test is performed on the accelerometer. The second self-test includes stimulating the accelerometer with a second self-test stimulation signal encoded with the second frequency, such that the accelerometer outputs a second signal.

Abstract: A method of detecting activity in a MEMS accelerometer captures an acceleration bias, measures acceleration at a predetermined time, calculates a change in acceleration using the measured acceleration and the acceleration bias, and compares the change in acceleration to a threshold to detect activity. A method of detecting inactivity uses a similar technique along with a timer. The method of detecting inactivity in a MEMS accelerometer captures an acceleration bias, measures acceleration at a predetermined time, calculates a change in acceleration using the measured acceleration and the acceleration bias, and compares the change in acceleration to a threshold to detect inactivity. The method further determines if the change in acceleration is less than the threshold and, if so, determines if a predetermined period of time has elapsed to detect inactivity.

Abstract: A packaged microchip has a lead frame with a die directly contacting at least a single, contiguous portion of the lead frame. The portion of the lead frame has a top surface forming a concavity and contacting the die. The packaged microchip also has mold material substantially encapsulating part of the top surface of the portion of the lead frame.

Abstract: An integrated circuit includes a substrate, a storage device formed in the substrate to hold bias settings, and operational blocks formed in the substrate, each operational block including an operational circuit and a charge pump to provide well bias voltages to the operational circuit in response to one or more of the bias settings. A method for testing an integrated circuit having two or more operational blocks includes: (a) determining a maximum operating speed of each of the blocks at a minimum supply voltage; (b) selecting a block that has a slow operating speed; (c) selecting a well bias to speed up the selected block; (d) selecting a supply voltage to meet a target operating frequency at the selected well bias and measuring power; (e) repeating acts (b)-(d) while the measured power is less than a baseline power; and (f) saving the selected well bias and supply voltage settings for operation of the integrated circuit.

Abstract: A successive approximation analog to digital converter comprising a plurality of capacitors which during a successive approximation conversion are selectively connectable to a first reference or a second reference under the command of a controller. During a conversion step where the connections of a given capacitor may be varied, the switches to the given capacitor are both placed in a high impedance state during a decision period of a comparator.

Abstract: A DMA controller includes at least one peripheral DMA channel for handling DMA transfers on a peripheral access bus; at least one memory DMA stream, including a memory destination channel and a memory source channel, for handling DMA transfers on first and second memory access buses; first and second address computation units for computing updated memory addresses for DMA transfers; first and second memory pipelines for supplying memory addresses to the first and second memory access buses, respectively, and for transferring data on the first and second memory access buses; and a multiplexer configured to supply first and second current memory addresses to selected ones of the first and second memory pipelines in response to a control signal.

Abstract: A system and apparatus for compensating cable losses in a video signal transmission system includes feedback circuits to determine the spectral attenuation of a received signal and to control an equalizer circuit to amplify selected frequencies of the received signal, and to determine the various times of arrival of two or more video signals and selectively adjust one or more delay lines to reduce the differences in their arrival times.

Abstract: An input biasing system for accommodating a floating power supply to the range of an input signal includes input terminals for receiving a input signal and a biasing circuit including a first impedance connected between one of the input terminals and a floating power supply and a second impedance connected between another of the input terminals and the ground of the floating power supply for bracketing the floating power supply about the input signal.